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* ARM: uniphier: remove unused umc_polling()Masahiro Yamada2016-02-29-9/+0
| | | | | | This function is unused. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: default to environment in eMMCMasahiro Yamada2016-02-29-0/+5
| | | | | | | Of the several boot devices supported, it looks like the eMMC is the most commonly used. Enable CONFIG_ENV_IS_IN_MMC by default. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add a command to find the first MMC (non-SD) deviceMasahiro Yamada2016-02-29-0/+34
| | | | | | | | | | | UniPhier SoC family supports both (e)MMC boot and SD card boot; however, both of them are handled in the same uclass. When booting from the eMMC, we want to know the device number of the (e)MMC, not SD. This command is useful to find the first MMC (non-SD) device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add eMMC boot supportMasahiro Yamada2016-02-29-0/+25
| | | | | | | | Export device nodes needed for eMMC boot (eMMC node, pinctrl, and clock) to the SPL DTB. CONFIG_SUPPORT_EMMC_BOOT is also necessary to use "mmc partconf" command. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boardsMasahiro Yamada2016-02-14-0/+16
| | | | | | | | | | Initial commit for PH1-Pro4 Ace and Sanji boards. Note: There are two variants for the Ace board in terms of the amount of DDR memory; 1GB or 2GB. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: adjust DDR clock delay line for ProXstream2Masahiro Yamada2016-02-14-2/+10
| | | | | | | | It turned out that DDR channel 2 was not working on ProXstream2 Vodka board. Add the missing ACBLDR0 register setting to adjust the delay between the clock lines and the address/command lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move cmd_ddrmphy.c to fix build errorMasahiro Yamada2016-02-14-0/+0
| | | | | | | If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada2016-02-14-1/+8
| | | | | | | | The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused header mio-regs.hMasahiro Yamada2016-02-14-20/+0
| | | | | | | | | This header is no longer used. This is the last file in arch/arm/mach-uniphier/include/mach/. At last, I've succeeded in eliminating the mach directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop unneeded EHCI pin mux settingsMasahiro Yamada2016-02-14-25/+0
| | | | | | | These pin mux settings are cared by the pinctrl drivers. Remove the ad-hoc code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: switch over to generic EHCI driverMasahiro Yamada2016-02-14-8/+8
| | | | | | | | | | | | The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does nothing special but set the base address and handle reset/clock. Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"), the generic one (drivers/usb/host/ehci-generic.c) can do those, too. We no longer need to stick to the dedicated driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoCMasahiro Yamada2016-02-14-2/+22
| | | | | | | | | | | | | | | | | | The USB boot code is too fat and complicated to be included in SPL (at least for now). So, it was implemented as a separate project (what we call USB-loader). The expected boot sequence is as follows: Boot ROM -> USB-loader -> SPL -> U-Boot proper The USB-loader loads the SPL and U-Boot proper from a USB memory onto the locked L2 cache. Then, SPL needs to copy the U-Boot proper to DRAM, so this mode looks like a NOR boot from the view of SPL. However, we want to distinguish between (genuine) NOR boot and USB boot in some places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add missing static qualifierMasahiro Yamada2016-02-14-1/+1
| | | | | | This function is for local use in the file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: create early page table at run-timeMasahiro Yamada2016-02-14-38/+94
| | | | | | | | | | | | | | | | | | UniPhier SoCs are not equipped with dedicated on-chip SRAM. Instead, locked outer cache is used as RAM area during the early boot stage where DRAM is not ready yet. This effectively means MMU must be always enabled while we are in SPL. Currently, the SPL image for UniPhier SoCs contains the page table statically defined at compile time. It has been a burden because the 16KB page table occupies a quarter memory footprint of the 64KB SPL image. Finally, there is no more room to implement new features in SPL. Setting aside the NOR boot mode, this issue can be solved by creating the page table onto RAM at run time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: change stack pointer address for SPLMasahiro Yamada2016-02-14-4/+1
| | | | | | | | | | | | | | | | | No special reason for the current stack address 0x0ff08000. Change it to 0x00100000 to simplify the init_page_table. There are two types of SoCs in terms of the load address of SPL. [1] PH1-sLD3, PH1-LD4, PH1-sLD8 SPL is loaded at 0x00040000-0x0004ffff [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b SPL is loaded at 0x00100000-0x0010ffff The new stack area (0x000f8000-0x00100000) should be safe for all the cases. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada2016-02-14-27/+53
| | | | | | | Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unneeded if conditionalsMasahiro Yamada2016-01-20-8/+2
| | | | | | | The if block does the same as the else block does. The conditional is not necessary at all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move UMC register macros to umc-regs.hMasahiro Yamada2016-01-20-48/+27
| | | | | | The umc-proxstream2.c defiens the same macros as in umc-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: set active ways to really enable outer cacheMasahiro Yamada2016-01-20-0/+2
| | | | | | Each way must be unlocked to make it effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix range invalidate for outer cacheMasahiro Yamada2016-01-20-0/+23
| | | | | | | If invalidate operation is invoked against a cache-unaliged region, the both ends of the region should be flushed, not invalidated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: factor out outer cache sync as a helper functionMasahiro Yamada2016-01-20-4/+8
| | | | | | Avoid repeating the same code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor outer cache operation slightlyMasahiro Yamada2016-01-20-2/+4
| | | | | | Improve readability without changing the behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add dump command for DDR Multi PHY registersMasahiro Yamada2016-01-13-0/+339
| | | | | | | | The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY which is not register-compatible with the former SoCs. Add a new command to support the register dump of this IP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6bMasahiro Yamada2016-01-13-0/+826
| | | | | | | | As mentioned in the log of commit 019df879a93e2 (ARM: uniphier: add ProXstream2 and PH1-LD6b support), the DRAM init code was missing for a long time. Finally, here it is. SPL works now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move headers out of include/mach directoryMasahiro Yamada2016-01-13-129/+188
| | | | | | | These headers are only included locally in arch/arm/mach-uniphier/. There is no reason to export them by putting in the mach/ directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move cmd_pinmon.c to boot-mode subdirectoryMasahiro Yamada2016-01-13-1/+2
| | | | | | | This command shows the boot mode pins, so it would be more at home in the boot-mode subdirectory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move cmd_ddrphy.c to dram subdirectoryMasahiro Yamada2016-01-13-1/+2
| | | | | | | This command shows the register dump of the DDR PHY, so it would be more at home in the dram subdirectory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: kill bogus header includesMasahiro Yamada2016-01-13-15/+0
| | | | | | These includes are not necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: set DTB file name to fdt_file environmentMasahiro Yamada2015-12-23-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | When we want to boot Linux with a DTB file downloaded from a TFTP server or somewhere, we need to know the file name to be downloaded. Assume the U-Boot configuration is shared among some similar boards. If they are similar enough, the difference only appears in device trees. The build procedure would be like this: - Board A: make foo_common_defconfig && make DEVICE_TREE=foo_board_a - Board B: make foo_common_defconfig && make DEVICE_TREE=foo_board_b - Board C: make foo_common_defconfig && make DEVICE_TREE=foo_board_c In this case, the U-Boot image contains nothing about the DTB file name it is running with. (CONFIG_DEFAULT_DEVICE_TREE is not helpful for this purpose because it is painful to change it from "make menuconfig" for each board.) This commit allows to lookup the DTB file name based on the compatible string and set it to "fdt_file" environment. Then "tftpboot $fdt_file" will download the file we want. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge umc/ and ddrphy/ into a single directoryMasahiro Yamada2015-12-23-15/+11
| | | | | | | | The UMC (Universal Memory Controller) and the DDR PHY block are highly related to each other. It is better to have both code in the same directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: display model number all the time on boot upMasahiro Yamada2015-12-23-2/+1
| | | | | | | | Both "Model 1" and "Model 2" are supported for ProXstream2 and PH1-LD6b boards. It is useful to show the model number in the boot banner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add macros and revision IDs for sLD11 and LD10Masahiro Yamada2015-12-23-1/+27
| | | | | | These are new SoCs from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: compile uniphier_get_board_param() for U-Boot properMasahiro Yamada2015-12-23-1/+1
| | | | | | | Compile this file for U-Boot proper as well as SPL, so that the U-Boot proper can call uniphier_get_board_param(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: split ProXstream2 board data and change DDR frequencyMasahiro Yamada2015-12-23-3/+17
| | | | | | | | | | The DDR3 memory chips on ProXstream2 boards support up to 2133 MHz, while only up to 1866MHz on PH1-LD6b boards. Split the board data structure and change the DDR frequency of ProXstream2 boards to 2133 MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: call uniphier_get_board_param() without FDT blobMasahiro Yamada2015-12-23-6/+7
| | | | | | | Move "gd->fdt_blob" from the caller to the callee so that this function can be used more easily. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add functions to get SoC model/revisionMasahiro Yamada2015-12-23-0/+15
| | | | | | | | | | | | | | We sometimes have to implement different code depending on the SoC revision. This commit adds functions to get the model/revision number. Note: Model number: incremented on major changes of the SoC Revision number: incremented on minor changes of the SoC The "Model 2" exists for PH1-sLD3, ProXstream2/PH1-LD6b. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: allow DDR function to return more precise error codeMasahiro Yamada2015-12-23-2/+3
| | | | | | | Return different error code depending on the reason so that the caller can know the cause of the failure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use BIT() macro for DDR PHY headerMasahiro Yamada2015-12-23-45/+46
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*Masahiro Yamada2015-12-23-4/+4
| | | | | | | The bit 27-24 of the DTCR register is described as RANKEN in the DDR PHY databook. Follow this abbreviation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add const qualifier to constant arrayMasahiro Yamada2015-12-23-1/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add static qualifiers to locally used functionsMasahiro Yamada2015-12-23-6/+6
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop UniPhier specific SMP codeMasahiro Yamada2015-11-11-61/+0
| | | | | | | | | | | The latest Linux can directly handle SMP operations for UniPhier SoCs without any help of U-boot. Drop the relevant code from U-boot. See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier: rework SMP operations to use trampoline code") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+48
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: fix init page table for ProXstream2/PH1-LD6b USB bootMasahiro Yamada2015-09-25-4/+2
| | | | | | | | Currently, the USB boot mode is supported by an external loader and U-boot proper image is put on the section 0. This commit allows access there. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add ProXstream2 and PH1-LD6b supportMasahiro Yamada2015-09-25-0/+567
| | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-Pro5 supportMasahiro Yamada2015-09-25-1/+346
| | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: allow to enable multiple SoCsMasahiro Yamada2015-09-25-429/+1068
| | | | | | | | | | | | | | | | | | | | Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: unify low-level debug init codeMasahiro Yamada2015-09-25-152/+115
| | | | | | | Move init code of low-level debug into a single file. This is helpful to create an image that runs on multiple SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix glitch signal problem for low-level debugMasahiro Yamada2015-09-25-20/+20
| | | | | | | | | | | | | | | | | | | Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: delete unneeded input enable for low-level debugMasahiro Yamada2015-09-25-5/+0
| | | | | | | The UART I/O ports for PH1-Pro4 has no input enable controlling. This code is useless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-12-29 14:36:09 +0000