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* ARM: uniphier: allow to enable multiple SoCsMasahiro Yamada2015-09-25-649/+0
| | | | | | | | | | | | | | | | | | | | Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: unify low-level debug init codeMasahiro Yamada2015-09-25-35/+0
| | | | | | | Move init code of low-level debug into a single file. This is helpful to create an image that runs on multiple SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix glitch signal problem for low-level debugMasahiro Yamada2015-09-25-7/+7
| | | | | | | | | | | | | | | | | | | Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: delete unneeded input enable for low-level debugMasahiro Yamada2015-09-25-5/+0
| | | | | | | The UART I/O ports for PH1-Pro4 has no input enable controlling. This code is useless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-2/+0
| | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.hMasahiro Yamada2015-09-25-27/+27
| | | | | | | To achieve the complete run-time configuration by device trees, ifdef conditionals in header files are not preferable. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: change the external bus address mappingMasahiro Yamada2015-09-25-6/+6
| | | | | | | | | | | | | | | | In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces 0x00000000 - 0x0fffffff 0x40000000 - 0x4fffffff are both mapped to the external bus (also called system bus), so either was OK. In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is assigned for the serial NOR interface. Going forward, use the latter for the external bus. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: drop DCC micro support card supportMasahiro Yamada2015-09-25-44/+1
| | | | | | | | | | Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: drop ad-hoc input enable settingsMasahiro Yamada2015-09-25-19/+1
| | | | | | | | | | These input enable settings are handled by the pinctrl drivers. Because the external bus pins are input-enabled by default, on-board devices such as LED still work fine even with this delayed input enabling. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop ad-hoc early pin-muxing settingsMasahiro Yamada2015-09-25-27/+1
| | | | | | | | | As the UniPhier serial driver had already switched to Drive Model and the pinctrl drivers are now enabled, these pin-muxing settings are properly handled by the pinctrl drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: enable SPL_OF_CONTROLMasahiro Yamada2015-08-31-16/+0
| | | | | | | | | | | | | Device Tree really improves code maintainability and is now available for SPL too. This is the state-of-the-art implementation in U-boot. The board files (platform data) are no longer needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: UniPhier: add pin mux setting for NAND CS1 of PH1-Pro4Masahiro Yamada2015-05-31-0/+2
| | | | | | | The chip select 1 of the NAND controller is available if you want to use, although the pins are shared with UART port 2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: replace <asm/io.h> with <linux/io.h>Masahiro Yamada2015-05-31-32/+24
| | | | | | | In the Linux coding style, it is recommended to include <linux/io.h> rather than <asm/io.h>. Follow this trend. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: move UART pin settings to SPLMasahiro Yamada2015-03-24-14/+30
| | | | | | | | The UniPhier platform is going to enable Driver Model and UART support on SPL. Move UART pin settings to early_pin_init(), which is called from SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: move platform devices to SPLMasahiro Yamada2015-03-24-1/+1
| | | | | | | | | | Since we do not have OF_CONTROL support for SPL, platform devices are necessary to enable Driver Model on SPL. To prepare for that, move platdevice.o to SPL and enable it by CONFIG_SPL_DM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initializationMasahiro Yamada2015-03-01-17/+0
| | | | | | | | | | This function was intended for MN2WS0235 (what we call PH1-Pro4TV). On that SoC, MPLL is already running on the power-on reset and it makes sense to stop the PLL at early boot-up. On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register, so this function has no point. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: consolidate MEMCONF setting codeMasahiro Yamada2015-03-01-10/+1
| | | | | | | | | | This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c. Merge the same code into a new file, memconf.c. The helper functions no longer have to be placed in the header file. Also, move them into memconf.c. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: support 1CS support card for all the UniPhier SoCsMasahiro Yamada2015-03-01-33/+46
| | | | | | | | | | | Two support card variants are used with UniPhier reference boards: - 1 chip select support card (original CPLD) - 3 chip selects support card (ARIMA-compatible CPLD) Currently, the former is only supported on PH1-Pro4, but it can be expanded to PH1-LD4, PH1-sLD8 with a little code change. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4Masahiro Yamada2015-03-01-0/+15
| | | | | | This is necessary to use the USB 3.0 host controllers on PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4Masahiro Yamada2015-03-01-0/+7
| | | | | | This is necessary to use the xHCI cores for PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: remove EHCI platform devicesMasahiro Yamada2015-03-01-10/+1
| | | | | | | | | | | Now UniPhier platform highly depends on Device Tree configuration (CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only used on main U-Boot, we can drop platform devices of the EHCI controllers. We still keep UART platform devices because they might be useful for SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
* ARM: UniPhier: enable STDMAC for EHCIMasahiro Yamada2015-03-01-1/+4
| | | | | | | Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: reset NAND core in SPL for non-NAND boot modeMasahiro Yamada2015-03-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: split clkrst_init() into two functionsMasahiro Yamada2015-03-01-8/+44
| | | | | | | | | | | | | | Split the current clkrst_init() into two functions: - early_clkrst_init(): called from SPL Deassert the reset signals of the memory controller and some other basic cores. - clkrst_init(): called from main U-boot Deassert the reset signals that are necessary for the access to peripherals etc. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*Masahiro Yamada2015-03-01-3/+3
| | | | | | Follow the register macros in the LSI specification book. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix SBC init codeMasahiro Yamada2015-03-01-5/+5
| | | | | | | | | Now UniPhier SoCs only work with CONFIG_SPL and the function sbc_init() is called from SPL. The conditional #if !defined(CONFIG_SPL_BUILD) has no point any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: fix comments in PH1-Pro4 SBC codeMasahiro Yamada2015-03-01-3/+3
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>Masahiro Yamada2015-03-01-18/+18
| | | | | | | | | Since commit 0e7368c6c426 (kbuild: prepare for moving headers into mach-*/include/mach), we can replace #include <asm/arch/*.h> with <mach/*.h> so we do not need to create the symbolic link during the build. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: UniPhier: move SoC sources to mach-uniphierMasahiro Yamada2015-03-01-0/+740
Move arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-12-27 15:27:47 +0000