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* ARM: uniphier: introduce flags to uniphier_board_data structureMasahiro Yamada2016-07-24-6/+12
| | | | | | | I need to add more board attributes, so the "flags" member will be handier than separate boolean ones. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-6/+7
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-LD11 SoC supportMasahiro Yamada2016-05-26-0/+137
| | | | | | This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename UMC register macros of PH1-LD20Masahiro Yamada2016-05-26-4/+4
| | | | | | Correct some register names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.hMasahiro Yamada2016-05-26-1/+1
| | | | | | | | This header will be shared between PH1-LD11 and PH1-LD20 (and hopefully new ARMv8 SoCs developed in the future), so umc64-regs.h would be a better fit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-LD20 SoC supportMasahiro Yamada2016-04-24-0/+421
| | | | | | This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada2016-04-01-9/+11
| | | | | | | Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop ifdef in ddrphy-regs.hMasahiro Yamada2016-03-24-75/+103
| | | | | | | | | The ifdef conditionals in header files prevent us from multi-SoC support in a single U-Boot image. Detect SoC specific parameters run-time rather than define them statically with an ifdef in ddrphy-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop PH1- prefix from CONFIG options and file namesMasahiro Yamada2016-03-24-10/+9
| | | | | | | | The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=yMasahiro Yamada2016-03-09-16/+2
| | | | | | | | The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data"). Fixes: 46abfcc99e04 ("ARM: uniphier: rework struct uniphier_board_data") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename variable for DRAM controller base addressMasahiro Yamada2016-02-29-114/+113
| | | | | | Rename the variable that contains the base address for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: deprecate umc_dram_init_{start, poll}Masahiro Yamada2016-02-29-23/+18
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused macros for UMC base addressesMasahiro Yamada2016-02-29-11/+0
| | | | | | | These macros are no longer used. These base addresses are SoC-dependent, so they should not be placed in the header. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework DRAM size handling in UMC init codeMasahiro Yamada2016-02-29-15/+15
| | | | | | | | | Currently, DRAM size is converted twice: size in byte -> size in Gbit -> enum Optimize the code by converting the "size in byte" into enum directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loopMasahiro Yamada2016-02-29-55/+59
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loopMasahiro Yamada2016-02-29-41/+49
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loopMasahiro Yamada2016-02-29-40/+43
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for PH1-LD4Masahiro Yamada2016-02-29-24/+55
| | | | | | Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support more DRAM use cases for PH1-sLD8Masahiro Yamada2016-02-29-6/+40
| | | | | | Support DDR3-1600 / 512MB DDR size. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for PH1-sLD8Masahiro Yamada2016-02-29-8/+29
| | | | | | Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor DDR-PHY init codeMasahiro Yamada2016-02-29-30/+40
| | | | | | | The if-else statements for the frequency-dependent register settings seem clumsy. Moving them to arrays would make it cleaner. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()Masahiro Yamada2016-02-29-16/+10
| | | | | | | The DDR PHY settings no longer depend on the DRAM size. Drop the argument from the init function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge DDR PHY init code for 3 SoCsMasahiro Yamada2016-02-29-167/+14
| | | | | | | | Now these three are almost the same. The only difference is the DTPR1 register dependency on the DRAM size, but it can be ignored. (It has already been ignored in PH1-sLD8 and PH1-Pro4.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add a field to specify DDR3+Masahiro Yamada2016-02-29-35/+39
| | | | | | | | | | | | | Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute). Default DDR3 spec for each SoC: PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: disable debug circuit clocks for PH1-Pro4Masahiro Yamada2016-02-29-2/+2
| | | | | | | These settings control the clocks around the memory controller. The debug ability is unneeded once it works properly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settingsMasahiro Yamada2016-02-29-60/+0
| | | | | | | | These settings were used only for the PH1-sLD3 and older SoCs. The PH1-LD4 and newer one just ignore them because their DDR-PHY take care of such timing parameters instead. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor UMC init code for ProXstream2Masahiro Yamada2016-02-29-45/+64
| | | | | | | | | | | | | | | | | Currently, a dummy value is defined for the UMC_SPCCTLA register when the DRAM size is zero. This seems weird because the controller does not need setting in the first place if the size is zero. Also, redefine enum dram_size to represent the DRAM size per 16-bit unit. This makes things simpler because the channel 0 and 1 are connected with 32-bit width DRAM, while the channel 2 is connected with 16-bit width one. I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_* for consistency) while I am here because SIZE_* might be easily mixed-up with the macros in include/linux/sizes.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use pr_err() where possibleMasahiro Yamada2016-02-29-5/+5
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: optimize ProXstream2 UMC init code with "for" loopMasahiro Yamada2016-02-29-22/+11
| | | | | | | Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rework struct uniphier_board_dataMasahiro Yamada2016-02-29-24/+24
| | | | | | | | This commit reworks "struct uniphier_board_data" with an array of DRAM channel data in it. It will allow further cleanups by means of "for" statements that iterate over the DDR channels. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unused umc_polling()Masahiro Yamada2016-02-29-9/+0
| | | | | | This function is unused. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: adjust DDR clock delay line for ProXstream2Masahiro Yamada2016-02-14-2/+10
| | | | | | | | It turned out that DDR channel 2 was not working on ProXstream2 Vodka board. Add the missing ACBLDR0 register setting to adjust the delay between the clock lines and the address/command lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move cmd_ddrmphy.c to fix build errorMasahiro Yamada2016-02-14-0/+329
| | | | | | | If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.cMasahiro Yamada2016-02-14-0/+6
| | | | | | | | The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram to build these commands. Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boardsMasahiro Yamada2016-02-14-27/+53
| | | | | | | Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove unneeded if conditionalsMasahiro Yamada2016-01-20-8/+2
| | | | | | | The if block does the same as the else block does. The conditional is not necessary at all. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move UMC register macros to umc-regs.hMasahiro Yamada2016-01-20-48/+27
| | | | | | The umc-proxstream2.c defiens the same macros as in umc-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add dump command for DDR Multi PHY registersMasahiro Yamada2016-01-13-0/+1
| | | | | | | | The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY which is not register-compatible with the former SoCs. Add a new command to support the register dump of this IP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6bMasahiro Yamada2016-01-13-0/+817
| | | | | | | | As mentioned in the log of commit 019df879a93e2 (ARM: uniphier: add ProXstream2 and PH1-LD6b support), the DRAM init code was missing for a long time. Finally, here it is. SPL works now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move headers out of include/mach directoryMasahiro Yamada2016-01-13-14/+320
| | | | | | | These headers are only included locally in arch/arm/mach-uniphier/. There is no reason to export them by putting in the mach/ directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: move cmd_ddrphy.c to dram subdirectoryMasahiro Yamada2016-01-13-0/+230
| | | | | | | This command shows the register dump of the DDR PHY, so it would be more at home in the dram subdirectory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge umc/ and ddrphy/ into a single directoryMasahiro Yamada2015-12-23-0/+862
The UMC (Universal Memory Controller) and the DDR PHY block are highly related to each other. It is better to have both code in the same directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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