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* sunxi: A64: enable SPLAndre Przywara2017-01-04-1/+1
| | | | | | | | | | | | | | | | Now that the SPL is ready to be compiled in AArch64 and the DRAM init code is ready, enable SPL support for the A64 SoC and in the Pine64 defconfig. For now we keep the boot0 header in the U-Boot proper, as this allows to still use boot0 as an SPL replacement without hurting the SPL use case. We disable FEL support for now by making its compilation conditional and disabling it for ARM64, as the code isn't ready yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: DRAM: fix H3 DRAM size display on aarch64Andre Przywara2017-01-04-1/+1
| | | | | | | | | | Fix the output of the DRAM size on AArch64 SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: H3/A64: fix non-ODT settingAndre Przywara2017-01-04-1/+7
| | | | | | | | | According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: A64: use H3 DRAM initialization code for A64 as wellJens Kuske2017-01-04-52/+162
| | | | | | | | | | | | | | The A64 DRAM controller is very similar to the H3 one, so the code can be reused with some small changes. This refactoring does not change the code size for the existing H3 part. [Andre: rework from #ifdefs to using socid parameters in static functions, minor fixes, merging in fixes from Jens] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: clocks: Use the correct pattern register for PLL11Philipp Tomsich2017-01-04-1/+1
| | | | | | | Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: H3: add DRAM controller single bit delay supportJens Kuske2017-01-04-27/+50
| | | | | | | | | | | | | | | | | | | | | | | So far the DRAM driver for the H3 SoC (and apparently boot0/libdram as well) only applied coarse delay line settings, with one delay value for all the data lines in each byte lane and one value for the control lines. Instead of setting the delays for whole bytes only allow setting it for each individual bit. Also add support for address/command lane delays. For the purpose of this patch the rules for the existing coarse settings were just applied to the new scheme, so the actual register writes don't change for the H3. Other SoCs will utilize this feature later properly. With a stock GCC 5.3.0 this increases the dram_sun8i_h3.o code size from 2296 to 2344 Bytes. [Andre: move delay parameters into macros to ease later sharing, use defines for numbers of delay registers, extend commit message] Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: H3: add and rename some DRAM contoller registersJens Kuske2017-01-04-17/+17
| | | | | | | | | The IOCR registers got renamed to BDLR to match the public documentation of similar controllers. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: H3: Rework MBUS priority setupPhilipp Tomsich2017-01-04-24/+64
| | | | | | | | | | | | | | | | | | | | | | | | | So far the MBUS priority setup was done by writing "magic" values taken from a DRAM controller register dump after a boot0 run. By peeking at the Linux (sic!) MBUS driver [1] from the Allwinner BSP kernel, we learned more about the actual meaning of those bits. Add macros and refactor the setup function to make the MBUS setup much more readable and meaningful. The actual values used now are a transformation of the values used before, which are assembled by the new code to result in the same register writes. So this rework does not change any settings, also the code size stays the same. The respective source files in the BSP kernel had a proper GPL header, so lifting this code and information into U-Boot is legal. [Andre: provide a convenience macro to fit definitions on one line] [1] https://github.com/longsleep/linux-pine64/blob/lichee-dev-v3.10.65/drivers/bus/sunxi_mbus.c Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: A64: do an RMR switch if started in AArch32 modeAndre Przywara2017-01-04-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC starts execution in AArch32 mode, and both the boot ROM and Allwinner's boot0 keep running in this mode. So U-Boot gets entered in 32-bit, although we want it to run in AArch64. By using a "magic" instruction, which happens to be an almost-NOP in AArch64 and a branch in AArch32, we differentiate between being entered in 64-bit or 32-bit mode. If in 64-bit mode, we proceed with the branch to reset, but in 32-bit mode we trigger an RMR write to bring the core into AArch64/EL3 and re-enter U-Boot at CONFIG_SYS_TEXT_BASE. This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode, so we can use the same start code for the SPL and the U-Boot proper. We use the existing custom header (boot0.h) functionality, but restrict the existing boot0 header reservation to the non-SPL build now. A SPL wouldn't need such header anyway. This allows to have both options defined and lets us use one for the SPL and the other for U-Boot proper. Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original ARM assembly code and instructions how to re-generate the encoded version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sun6i: Restrict some register initialization to Allwinner A31 SoCAndre Przywara2017-01-04-1/+5
| | | | | | | | | | | | | | | | | | | These days many Allwinner SoCs use clock_sun6i.c, although out of them only the (original sun6i) A31 has a second MBUS clock register. Also the requirement for setting up the PRCM PLL_CTLR1 register to provide the proper voltage seems to be a property of older SoCs only as well. Restrict the MBUS initialization to this SoC only to avoid writing bogus values to (undefined) registers in other chips. I can only verify that the PLL voltage setup is not needed for H3 and A64, so for now we only spare those two SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* sunxi: fix SID read on H3Icenowy Zheng2016-12-20-0/+44
| | | | | | | | | | | | | H3 SID controller has some bug, which makes the initial SID value at SUNXI_SID_BASE wrong when boot. Change the SID retrieve code to call the SID Controller directly on H3, which can get the correct value, and also fix the SID value at SUNXI_SID_BASE, so that it can be used by further operations. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spl: sunxi: Drop spl_board_announce_boot_device()Simon Glass2016-12-09-9/+0
| | | | | | This function is not used anymore. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: Add a name to the SPL load-image methodsSimon Glass2016-12-09-1/+1
| | | | | | | | | | | It is useful to name each method so that we can print out this name when using the method. Currently this happens using a separate function. In preparation for unifying this, add a name to each method. The name is only available if we have libcommon support (i.e can use printf()). Signed-off-by: Simon Glass <sjg@chromium.org>
* sunxi: add initial clock setup for sun9i for SPLPhilipp Tomsich2016-10-30-2/+144
| | | | | | | | | | This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Enable SMP mode for the boot CPU on sun9i (A80)Philipp Tomsich2016-10-30-1/+2
| | | | | | | | | | Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: add gtbus-initialisation for sun9iPhilipp Tomsich2016-10-30-1/+55
| | | | | | | | | | | | | | | | | On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: DRAM initialisation for sun9iPhilipp Tomsich2016-10-30-0/+962
| | | | | | | | | | | | | | | This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: A64: enable USB supportAmit Singh Tomar2016-10-30-2/+3
| | | | | | | | | | | | | | | | Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Fix H3 DRAM impedance calibration on rev. A chipsJens Kuske2016-10-10-21/+43
| | | | | | | | | | | | | | | | H3 seems to have a silicon bug breaking the impedance calibration. This is currently worked around in software by multiple steps combining the results to replace the wrong values. Revision A chips need a different workaround, which is present in the vendor bootloader too, but got overlooked in lack of information and affected boards till now. This commit adds a simplified version without correction factor, which would be 1.00 for all known boards anyway. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* spl: Pass spl_image as a parameter to load_image() methodsSimon Glass2016-10-06-1/+2
| | | | | | | | | Rather than having a global variable, pass the spl_image as a parameter. This avoids BSS use, and makes it clearer what the function is actually doing. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: Convert spl_board_load_image() to use linker listSimon Glass2016-10-06-1/+4
| | | | | | | | Add a linker list declaration for this method and remove the explicit switch() code. Update existing users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: Convert boot_device into a structSimon Glass2016-10-06-1/+1
| | | | | | | | | | | At present some spl_xxx_load_image() functions take a parameter and some don't. Of those that do, most take an integer but one takes a string. Convert this parameter into a struct so that we can pass all functions the same thing. This will allow us to use a common function signature. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi: musb: Power off OTG port VBUS when disabledChen-Yu Tsai2016-09-17-7/+0
| | | | | | | | | | | | | | The Linux kernel musb driver expects VBUS to be off while initializing musb. Having it on results in a repeating string of warnings, followed by an unusable peripheral. The peripheral is only usable after physically removing the OTG adapter, letting musb reset its state. This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never power off the usb ports") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Tune H3 DRAM PLL to improve lock timeJens Kuske2016-08-26-0/+6
| | | | | | | | | | | | The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: Rework and correct barrier definitionsTom Rini2016-08-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-2/+4
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * armv8: mmu: Add support of non-identical mappingYork Sun2016-07-15-2/+4
| | | | | | | | | | | | | | Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping. Signed-off-by: York Sun <york.sun@nxp.com>
* | sunxi: Use BROM stored boot_media value to determine our boot-sourceHans de Goede2016-07-15-23/+11
| | | | | | | | | | | | | | | | | | Now that we know that the BROM stores a value indicating the boot-source at the beginning of SRAM, use that instead of trying to recreate the BROM's boot probing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+5
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-26-1/+1
| | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* sunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"Bernhard Nortmann2016-05-25-0/+9
| | | | | | | | | | | This addresses a cosmetic issue when booting a sunxi device over USB (FEL mode), where the SPL currently would just print "Trying to boot from ". The patch fixes that to properly read "Trying to boot from FEL". Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: power: add AXP809 supportChen-Yu Tsai2016-05-25-3/+4
| | | | | | | | The A80 uses the AXP809 as its primary PMIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-12-1/+1
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* sunxi: mctl_mem_matches: Add missing memory barrierHans de Goede2016-04-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this. This avoids mctl_mem_matches always returning false in some cases, which was resulting in: U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26) DRAM: 1024 MiB U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology CPU: Allwinner A23 (SUN8I) DRAM: 512 MiB Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add INITIAL_USB_SCAN_DELAY Kconfig optionHans de Goede2016-04-12-0/+7
| | | | | | | | | Some boards have on board usb devices which need longer than the USB spec's 1 second to connect from board powerup. Add a config option which when non 0 adds an extra delay before the first usb bus scan. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-01-1/+32
| | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-01-4/+4
| | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Move cpu independent code to mach directoryAlexander Graf2016-04-01-0/+4973
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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