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* arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen2015-11-03-3/+3
| | | | | | | The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: enable data/inst prefetch and shared override in the L2Dinh Nguyen2015-10-17-0/+12
| | | | | | | | | | | | | | | | | | | | Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config filesDinh Nguyen2015-09-23-2/+2
| | | | | | | | | Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Add support for the Terasic DE-0 Atlas boardDinh Nguyen2015-09-04-0/+7
| | | | | | | Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Add support for DENX MCV SoM and MCVEVK boardMarek Vasut2015-09-04-0/+7
| | | | | | | | Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Add support for Terasic SoCkit boardMarek Vasut2015-09-04-0/+7
| | | | | | | | Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Do not call board_init_r() from board_init_f()Marek Vasut2015-09-04-2/+0
| | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the SoCFPGA SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Assure ISWGRP 0 and 1 are initedMarek Vasut2015-09-04-1/+7
| | | | | | | | | | This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* mmc: dw_mmc: Probe the MMC from OFMarek Vasut2015-09-04-9/+2
| | | | | | | | | | | | | Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-23-6/+4
| | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-23-30/+8
| | | | Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Add qts-filter.sh scriptMarek Vasut2015-08-23-0/+205
| | | | | | | | | Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-23-2/+2
| | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Unbind CPU type from board typeMarek Vasut2015-08-23-8/+18
| | | | | | | | | | | | | | | | | | | The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-23-0/+545
| | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Fix delay in clock managerMarek Vasut2015-08-23-7/+5
| | | | | | | | This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Fix delay in freeze controllerMarek Vasut2015-08-23-7/+5
| | | | | | | | | | | | Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Add support for printing FPGA typeDinh Nguyen2015-08-08-2/+65
| | | | | | | | | | Add code which uses the new functions for obtaining FPGA ID from the scan manager. This new code prints the FPGA model attached to the SoCFPGA during boot and sets environment variable "fpgatype", which can be used to determine the FPGA model in U-Boot scripts. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Add code to get FPGA IDDinh Nguyen2015-08-08-0/+56
| | | | | | | Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code uses the scan manager to send jtag pulses that will return the FPGA ID. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: scan: Factor out IO chain programmingMarek Vasut2015-08-08-71/+42
| | | | | | | | Factor out the code which sends JTAG instruction followed by data into separate function to tidy the code up a little. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: scan: Clean up horrible macrosMarek Vasut2015-08-08-72/+17
| | | | | | | | | | | Clean up the horrible macros present in the scan_manager.h . Firstly, the function scan_mgr_io_scan_chain_prg() is static, yet all the macros are used only within it, thus there is no point in having them in the header file. Moreover, the macros are just making the code much less readable, so remove them instead. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: scan: Introduce generic JTAG accessorMarek Vasut2015-08-08-41/+63
| | | | | | | | | Introduce generic function for accessing the JTAG scan chains in the SCC manager. Make use of this function throughout the SCC manager to replace the ad-hoc writes to registers and make the code less cryptic. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: scan: Clean up scan_chain_engine_is_idle()Marek Vasut2015-08-08-28/+34
| | | | | | | | | | Rework this function so it's clear that it is only polling for certain bits to be cleared. Add kerneldoc. Fix it's return value to be either 0 on success and -ETIMEDOUT on error and propagate this through the scan manager code. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-08-0/+17
| | | | | | | | | | | Introduce structure socfpga_sdram_misc_config to wrap the remaining misc configuration values in board file. Again, introduce a function, socfpga_get_sdram_misc_config(), which returns this the structure. This is almost the final step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-08-0/+19
| | | | | | | | | | | Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-08-0/+64
| | | | | | | | | | | Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-08-0/+3
| | | | | | | | | | Introduce two wrapper functions, socfpga_get_seq_ac_init() and socfpga_get_seq_inst_init() to avoid direct inclusion of the sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS generated files. This reduces namespace pollution again. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Clean up mach/sdram.hMarek Vasut2015-08-08-3/+1
| | | | | | | | Zap non-existent functions and place function prototypes at the beginning of the header file. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut2015-08-08-0/+42
| | | | | | | | | | Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8Marek Vasut2015-08-08-1/+1
| | | | | | Fix the return value so that standard errno return values can be used. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Add temporary workaround for missing SD/MMC patchesMarek Vasut2015-08-08-0/+6
| | | | | | | | | | | | Add a small workaround into the platform code which forces the SDMMC into 8-bit mode (the default configuration for all socfpga platforms) to work around breakage caused by missing patches in mainline which switch the probing of SD/MMC to OF instead of static configuraiton. The patches will hit mainline after the SPL series, so to avoid build issues, add this small temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESSMarek Vasut2015-08-08-1/+1
| | | | | | | Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS in the code. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: config: Move SPL GD and malloc to RAMMarek Vasut2015-08-08-0/+3
| | | | | | | | | | | Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Reset ethernet from OFMarek Vasut2015-08-08-19/+49
| | | | | | | | | | | Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc hardcoded values in the U-Boot code. Since we don't have a proper reset framework in place yet, we have to do this slightly ad-hoc parsing of the OF tree instead. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: misc: Probe ethernet GMAC from OFMarek Vasut2015-08-08-3/+1
| | | | | | | | | The GMAC can now be probed from OF, so enable DM ethernet and remove the old ad-hoc designware_initialize() invocation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* arm: socfpga: misc: Export bootmode into environment variableMarek Vasut2015-08-08-11/+23
| | | | | | | | setenv an environment variable called "bootmode" , which contains the board boot mode. This can be in turn used in scripts to determine from where to load kernel and such. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Add support for printing boot modeMarek Vasut2015-08-08-0/+13
| | | | | | | Add support for printing from which device the SoCFPGA board booted. This decodes the BSEL settings and prints it in human readable form. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: misc: Fix warm resetMarek Vasut2015-08-08-0/+10
| | | | | | | | | | | | | | Write necessary magic value into the Warm Boot from ON-Chip RAM group Enable register to enable Warm reset support. Instead of doing this in the reset_cpu() function, we do it in arch early init to avoid breaking old kernel code which expects this magic value to be already written into this register. This magic is originally excavated from common/spl/spl.c in the u-boot port from altera, where this value was written just before the SPL jumped to actual U-Boot in the RAM. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for selecting boot device from BSELMarek Vasut2015-08-08-12/+23
| | | | | | | | Rework spl_boot_device() such that it reads the BSEL settings from system manager and decides from where to load U-Boot based on this information. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from QSPIMarek Vasut2015-08-08-1/+4
| | | | | | | Add code and configuration options to support booting from QSPI NOR. Enable support for booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add support for booting from SD/MMCMarek Vasut2015-08-08-0/+17
| | | | | | | | | | Add code and configuration options to support booting from RAW SD/MMC card as well as for ext4/vfat filesystems. Enable support for booting from SD/MMC card, but don't enable the filesystem support just yet to retain compatibility with old SoCFPGA card format. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Remove custom linker scriptMarek Vasut2015-08-08-45/+0
| | | | | | | | Remove the custom SPL linker script, use the generic one instead. The custom script doesn't bring in anything new and is only burden to maintain. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Merge spl_board_init() into board_init_f()Marek Vasut2015-08-08-17/+12
| | | | | | | | | | The code in spl_board_init() should have been in board_init_f() from the beginning, since it is code which configures system and then starts DRAM. Thus, it cannot be in spl_board_init(), which is called from board_init_r() , which already expects a working DRAM. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Add missing reset logicMarek Vasut2015-08-08-1/+9
| | | | | | | | Make sure that all the peripherals are correctly reset and then brought out of reset in the SPL. Not going through proper reset cycle might leave the IP blocks in inconsistent state. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Configure SCU and NIC-301 earlyMarek Vasut2015-08-08-0/+22
| | | | | | | | | Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register must be configured, so we can access all peripherals. The NIC-301 must be configured so that the BootROM is not mapped into the SDRAM address space. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: spl: Toggle warm reset config I/O bitMarek Vasut2015-08-08-0/+5
| | | | | | | Synchronise the SPL behavior with the original Altera code and toggle the Warm Reset Config I/O bit accordingly. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-4/+7
| | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()Marek Vasut2015-08-08-5/+9
| | | | | | | | Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(), which allows both enabling and disabling the warm reset config I/O functionality. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-31/+11
| | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()Marek Vasut2015-08-08-13/+26
| | | | | | | | | It is sufficient to pass in the scan chain ID into the function to determine the remaining two parameters, so drop those params and determine them locally in the function. The big-ish switch in the function is temporary and will be replaced by a proper function call in subsequent patch. Signed-off-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-11-20 18:34:57 +0000