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* SPL: add support to boot from a partition typeDalon Westergreen2017-02-17-0/+6
| | | | | | | | | | | | | the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* arm: socfpga: set the mpuclk divider in the Altera group registerDinh Nguyen2017-02-08-0/+9
| | | | | | | | | | | | | The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* Kconfig: Migrate BOARD_LATE_INIT to a selectTom Rini2017-01-24-0/+1
| | | | | | | | | This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
* qts-filter.sh: strip DOS line endings and handle continuation linesBill Randle2016-12-06-15/+32
| | | | | | | | | Some Altera Quartus generated files have long lines that are split with a '\' at the end of the line. It also wOn Windows, rites files in DOS format, which can confuse some of the processing scripts in this file. This patch solves both issues. Signed-off-by: Bill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
* ARM: socfpga: Add boot0 hook to prevent SPL corruptionMarek Vasut2016-12-06-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* socfpga: add support for Terasic DE1-SoC boardAnatolij Gustschin2016-12-06-0/+7
| | | | | | | | Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
* Fix spelling of "resetting".Vagrant Cascadian2016-10-31-1/+1
| | | | | | | | Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-2/+15
| | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-2/+2
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SPL_WATCHDOG_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_SPI_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_SPI_FLASH_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_NAND_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_MMC_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBGENERIC_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBDISK_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SPL_LIBCOMMON_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-26-1/+1
| | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* ARM: socfpga: Sort Kconfig entriesMarek Vasut2016-06-08-4/+4
| | | | | | | | Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* ARM: socfpga: add support for IS1 boardPavel Machek2016-06-08-0/+6
| | | | | | | | This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Add samtec VIN|ING boardMarek Vasut2016-06-01-0/+7
| | | | | | | | | | | | | | | | | Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
* socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-06-1/+1
| | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
* arm: socfpga: Nuke useless includeMarek Vasut2016-04-10-13/+0
| | | | | | | | | | The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* arm: socfpga: Handle phy-mode OF property for GMACsMarek Vasut2016-04-10-3/+36
| | | | | | | | | | | | | | | Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space, so PHYs connected in another modes did not work. This patch fixes support for configurations where the ethernet PHYs are connected over MII/GMII/RMII interfaces by parsing the phy-mode OF property of the GMACs and configuring the ethernet registers in sysmgr space accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Fix ethernet reset handlingMarek Vasut2016-02-24-2/+7
| | | | | | | | | | | | | | | | | | The following patch caused cpu_eth_init() to not be called anymore for DM-capable boards: commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d Date: Sun Jan 17 14:51:56 2016 -0700 net: Don't call board/cpu_eth_init() with driver model This breaks ethernet on SoCFPGA, since we use that function to un-reset the ethernet blocks. Invoke the ethernet reset function from arch_misc_init() instead to fix the breakage. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
* arm: socfpga: Remove bashisms from qts filterMarek Vasut2016-02-24-7/+7
| | | | | | | | | | Weed out bashisms from the script. The echo -e does not work in dash, which is the default /bin/sh in debian . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com>
* socfpga: Modify qts-filter args to allow input for bsp generated files and ↵Dalon Westergreen2016-01-16-31/+45
| | | | | | | | | | | | quartus project directories The hps_isw_handoff and bsp/generated folders are typically not in the same path.This patch adds support for specifying the different input directories for the bsp and quartus projects. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* arm: socfpga: Unreset NAND in U-BootMarek Vasut2015-12-22-0/+4
| | | | | | | | Make sure the NAND reset is not asserted in full U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* arm: socfpga: Unreset NAND in SPLMarek Vasut2015-12-22-0/+1
| | | | | | | | If the system boots from NAND, make sure to de-assert the NAND IP reset, otherwise the system will get stuck. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Define NAND reset bitMarek Vasut2015-12-22-1/+2
| | | | | | | Define the NAND reset bit and fix the ordering of the macros. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Actually enable L2 cacheMarek Vasut2015-12-22-2/+11
| | | | | | | | | The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* arm: socfpga: fix up a questionable macro for SDMMCDinh Nguyen2015-12-20-3/+7
| | | | | | | | Move the macro into the socfpga_dwmci_clksel(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> [fix parenthesis in the sdmmc_mask]
* arm: socfpga: remove building scan managerDinh Nguyen2015-12-20-2/+3
| | | | | | | | The scan manager is not needed for the Arria10. Edit the makefile to build the scan manager for arria5 and cyclone5 only. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de>
* arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config propertyDinh Nguyen2015-12-20-0/+5
| | | | | | | | | In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Introduce common board codeMarek Vasut2015-12-20-1/+65
| | | | | | | | | | The SoCFPGA has reached a point where every single board code become the same, since each and every single board is probed equally from OF. Move the common board code into arch/arm/mach-socfpga/ . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Remove cpu_mmc_init()Marek Vasut2015-12-07-11/+0
| | | | | | | | | | | | This function triggers the registration of the dwmmc driver on SoCFPGA, but this is not needed in case the driver is correctly probed from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* arm: socfpga: Add SoCFPGA SR1500 boardStefan Roese2015-12-07-0/+6
| | | | | | | | | | | | | | | The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* arm: socfpga: Repair SoCrates boardMarek Vasut2015-11-30-0/+7
| | | | | | | | | | | | | | This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
* ARM: socfpga: rename the cyclone5 and arria5 base address fileDinh Nguyen2015-11-30-0/+0
| | | | | | | | | When adding support for the Arria10 platform, we're going to name the file base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h to be base_addr_ac5.h for the Arria5 and Cyclone5 platform. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ARM: socfpga: arria10: add base address map for Arria10Dinh Nguyen2015-11-30-0/+45
| | | | | | | Add the base address map for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Reviewed-by: Marek Vasut <marex@denx.de>
* arm: socfpga: reset: FIX address of tstscratch registerPhilipp Rosenberger2015-11-30-0/+1
| | | | | | | | | | | The Cyclone V Hard Processor System Technical Reference Manual in the chapter about the Reset Manager Module Address Map stats that the offset of the tstscratch register ist 0x54 not 0x24. Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02 page 3-17 Reset Manager Module Address Map Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
* arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit definesDinh Nguyen2015-11-03-3/+3
| | | | | | | The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register, not the mpumodrst. So the bank for these reset bits should be 1, not 0. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: enable data/inst prefetch and shared override in the L2Dinh Nguyen2015-10-17-0/+12
| | | | | | | | | | | | | | | | | | | | Update the L2 AUX CTRL settings for the SoCFPGA. Enabling D and I prefetch bits helps improve SDRAM performance on the platform. Also, we need to enable bit 22 of the L2. By not having bit 22 set in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config filesDinh Nguyen2015-09-23-2/+2
| | | | | | | | | Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Add support for the Terasic DE-0 Atlas boardDinh Nguyen2015-09-04-0/+7
| | | | | | | Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Add support for DENX MCV SoM and MCVEVK boardMarek Vasut2015-09-04-0/+7
| | | | | | | | Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Add support for Terasic SoCkit boardMarek Vasut2015-09-04-0/+7
| | | | | | | | Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Do not call board_init_r() from board_init_f()Marek Vasut2015-09-04-2/+0
| | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the SoCFPGA SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Assure ISWGRP 0 and 1 are initedMarek Vasut2015-09-04-1/+7
| | | | | | | | | | This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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