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* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-1/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: correct sdram settingChris Zhong2016-03-10-7/+7
| | | | | | | | | | | | | | | The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, and it expects uboot to store the value using a same protocol. But now the ddr setting value is different with DMC, so if you enable the DMC, system would crash in kernel. Correct the sdram setting here, according to the requirements of kernel. [0] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c Signed-off-by: Chris Zhong <zyw@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: make configure_emmc() empty for Firefly-RK3288FUKAUMI Naoki2016-03-10-1/+1
| | | | | | | | | | | | | | | | | | | | | on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for Firefly-RK3288. (it's fine for Rock2) $ gcc --version gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204 Copyright (C) 2015 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img Warning: SPL image is too large (size 0x80d0) and will not boot to reduce size of SPL image, this patch makes configure_emmc() empty for Firefly-RK3288 as same as Rock2. Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-By: Vagrant Cascadian <vagrant@debian.org>
* rockchip: rk3036: change ddr frequency to 400MLin Huang2016-03-10-1/+1
| | | | | | | | | emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add support for Raxda Rock 2Simon Glass2016-01-21-0/+12
| | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+45
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Drop MMC support code when not neededSimon Glass2016-01-21-2/+4
| | | | | | When the board does not use MMC SPL this code is a waste of space. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-21-14/+3
| | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-21-2/+2
| | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add a simple 'clock' commandSimon Glass2016-01-21-0/+24
| | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Don't skip low-level initSimon Glass2016-01-21-0/+8
| | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2016-01-21-29/+0
| | | | | | | | | | | | The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: reset: Use the rk_clr/setreg() interfaceSimon Glass2016-01-21-2/+2
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use the rk_clr/setreg() interfaceSimon Glass2016-01-21-4/+3
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Avoid using MMC code when not booting from MMCSimon Glass2016-01-21-0/+2
| | | | | | This saves some code space in SPL which is useful on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Use the debug UART on rk3036Simon Glass2016-01-12-65/+8
| | | | | | | Rather than using a new debug UART implementation, use the standard one provided by U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
* rockchip: Add basic support for kylin boardhuang lin2015-12-13-0/+4
| | | | | | | | | kylin board use rk3036 SOC, 512M sdram, 8G emmc. This add some basic files required to allow the board to output serial message and can run command(mmc info etc). Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036 sdram setting cs1_row when rank larger than 1huang lin2015-12-13-1/+5
| | | | | | | | only rank large than 1, we will use cs1_row, so check rank, when rank larger than 1, we set the cs1_row. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "rockchip: Add max spl size & spl header configs"Jeffy Chen2015-12-13-27/+0
| | | | | | | This reverts commit 10b4615f9d7e177ec7fe644fbb2616e0e0956f6e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons2015-12-01-7/+0
| | | | | | | | | | | This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro2015-12-01-0/+3
| | | | | | | | | | | | | | | | | Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add max spl size & spl header configsJeffy Chen2015-12-01-0/+27
| | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-01-0/+14
| | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-2/+104
| | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+766
| | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add early uart driverhuang lin2015-12-01-0/+64
| | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
| | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add config decide whether to build common.chuang lin2015-12-01-1/+1
| | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-01-1/+1
| | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-01-3/+3
| | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add timer driverhuang lin2015-12-01-19/+51
| | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* ns16550: unify serial_rockchipThomas Chou2015-11-21-3/+0
| | | | | | | | | Unify serial_rockchip, and use the generic binding. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Reconfigure the malloc based to point to system memorySjoerd Simons2015-10-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | When malloc_base initially gets setup in the SPL it is based on the current (early) stack pointer, which for rockchip is pointing into SRAM. This means simple memory allocations happen in SRAM space, which is somewhat unfortunate. Specifically a bounce buffer for the mmc allocated in SRAM space seems to cause the mmc engine to stall/fail causing timeouts and a failure to load the main u-boot image. To resolve this, reconfigure the malloc_base to start at the relocated stack pointer after DRAM has been setup. For reference, things did work fine on rockchip before 596380db was merged to fix memalign_simple due to a combination of rockchip SDRAM starting at address 0 and the dw_mmc driver not checking errors from bounce_buffer_start. As a result, when a bounce buffer needed to be allocated mem_align simple would fail and return NULL. The mmc driver ignored the error and happily continued with the bounce buffer address being set to 0, which just happened to work fine.. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for jerrySimon Glass2015-09-02-0/+10
| | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-02-0/+10
| | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add core SoC start-up codeSimon Glass2015-09-02-0/+421
| | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SDRAM initSimon Glass2015-09-02-0/+879
| | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add a simple syscon driverSimon Glass2015-09-02-0/+26
| | | | | | Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SoC reset driverSimon Glass2015-09-02-0/+54
We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-06 00:15:32 +0000