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* Convert CONFIG_SPL_SERIAL_SUPPORT to KconfigSimon Glass2016-09-16-0/+3
| | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers/sysreset: group sysreset driversMax Filippov2016-08-12-46/+0
| | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* configs: rockchip: remove no use MACROKever Yang2016-07-31-3/+0
| | | | | | | | The CONFIG_ROCKCHIP_COMMON and CONFIG_SPL_ROCKCHIP_COMMON are no use now, remove them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* board: move all the rockchip board in one folderKever Yang2016-07-25-2/+2
| | | | | | | | | | | The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them to 'rockchip' which is a real _vendor_ name, and meet the architecure 'board/<vendor>/<board-name>/'. More boards from rockchip like evb_rk3288, evb_rk3399 will comes later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
* rockchip: add option to change method of loading u-bootXu Ziyuan2016-07-25-33/+0
| | | | | | | | | | | | | | | | | If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
* Rename reset to sysresetStephen Warren2016-05-26-10/+10
| | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: change ddr frequency to 400MLin Huang2016-03-10-1/+1
| | | | | | | | | emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic support for kylin boardhuang lin2015-12-13-0/+4
| | | | | | | | | kylin board use rk3036 SOC, 512M sdram, 8G emmc. This add some basic files required to allow the board to output serial message and can run command(mmc info etc). Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036 sdram setting cs1_row when rank larger than 1huang lin2015-12-13-1/+5
| | | | | | | | only rank large than 1, we will use cs1_row, so check rank, when rank larger than 1, we set the cs1_row. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "rockchip: Add max spl size & spl header configs"Jeffy Chen2015-12-13-6/+0
| | | | | | | This reverts commit 10b4615f9d7e177ec7fe644fbb2616e0e0956f6e Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add max spl size & spl header configsJeffy Chen2015-12-01-0/+6
| | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-01-0/+14
| | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-01-0/+36
| | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+766
| | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-01-1/+22
| | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add Soc reset driverhuang lin2015-12-01-0/+55
We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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