| Commit message (Collapse) | Author | Age | Lines | |
|---|---|---|---|---|
| * | rockchip: rk3036: Add core Soc start-up code | huang lin | 2015-12-01 | -0/+1 |
| | | | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288 | |||
| * | rockchip: add rk3036 sdram driver | huang lin | 2015-12-01 | -0/+2 |
| | | | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> | |||
| * | rockchip: rk3036: Add a simple syscon driver | huang lin | 2015-12-01 | -1/+1 |
| | | | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> | |||
| * | rockchip: rk3036: Add Soc reset driver | huang lin | 2015-12-01 | -0/+10 |
| We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> | ||||
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index : arm-boot/u-boot-imx.git | |
| U-boot NXP imx6 | git@iatec.biz |
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