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* arm: mvebu: Move some defines to common include fileStefan Roese2016-01-14-0/+6
* net: mvneta: Convert to driver modelStefan Roese2016-01-14-28/+0
* arm: mvebu: Add SPI driver model supportStefan Roese2016-01-14-3/+4
* arm: mvebu: Add DM and OF_CONTROL support to SPLStefan Roese2016-01-14-65/+27
* arm: mvebu/kirkwood: Use common timer functionsStefan Roese2016-01-14-124/+17
* arm: mvebu: Configure ARP timeout and retry countStefan Roese2015-11-29-0/+2
* arm: mvebu: a38x: serdes specification cleanupKevin Smith2015-11-17-52/+48
* arm: mvebu: a38x: Add const to some function callsKevin Smith2015-11-17-7/+7
* arm: mvebu: a38x: Remove unsupported topologiesKevin Smith2015-11-17-1315/+0
* compat: Remove is_power_of_2() definitionFabio Estevam2015-11-05-1/+1
* arm: mvebu: Add DM (driver model) supportStefan Roese2015-10-21-3/+0
* arm: mvebu: Do not call board_init_r() from board_init_f()Stefan Roese2015-10-21-2/+0
* arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPLStefan Roese2015-10-21-12/+19
* arm: mvebu: Add option to use UART xmodem protocol via kwbootStefan Roese2015-10-21-1/+54
* arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig fileStefan Roese2015-10-20-0/+21
* arm: mvebu: timer.c: Explicitly move "init_done" var to data sectionStefan Roese2015-10-01-1/+1
* arm: mvebu: Fix internal register config on A38xStefan Roese2015-10-01-14/+22
* bitops: introduce BIT() definitionHeiko Schocher2015-09-11-2/+0
* pci: mvebu: Add PCIe driverAnton Schubert2015-08-17-8/+0
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-17-6/+139
* arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()Stefan Roese2015-08-17-9/+21
* arm: mvebu: Display ECC enabled / disabled upon bootupStefan Roese2015-08-17-0/+19
* arm: mvebu: Enable USB EHCI support on Armada XPStefan Roese2015-08-17-0/+44
* arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-17-2/+40
* arm: mvebu: Disable MBUS error propagationStefan Roese2015-08-17-0/+6
* arm: mvebu: Flush caches and disable MMU only on A38xStefan Roese2015-08-17-7/+19
* arm: mvebu: Setup the MBUS bridge registersStefan Roese2015-08-17-0/+58
* arm: mvebu: Change MBUS base addresses and sizesStefan Roese2015-08-17-10/+16
* arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INITStefan Roese2015-08-17-2/+0
* arm: mvebu: Add SPL SDIO/MMC boot supportStefan Roese2015-07-24-1/+12
* arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese2015-07-23-0/+4
* arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese2015-07-23-2/+2
* arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdrStefan Roese2015-07-23-0/+5204
* arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directoryStefan Roese2015-07-23-1/+2
* arm: mvebu: Disable MMU before changing register base addressStefan Roese2015-07-23-0/+18
* arm: mvebu: spl.c: Add call to board_early_init_f()Stefan Roese2015-07-23-0/+7
* arm: mvebu: Use default reg base address for SPL on A38xStefan Roese2015-07-23-0/+10
* arm: mvebu: Call timer_init early before PHY and DDR initStefan Roese2015-07-23-0/+9
* arm: mvebu: add Armada XP SATA supportAnton Schubert2015-07-23-0/+1
* usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-10-0/+1
* arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese2015-07-10-0/+56
* arm: mvebu: Add SDIO/SDHCI support for Armada A38xStefan Roese2015-07-10-0/+24
* arm: mvebu: Update CBAR with SOC regs baseKevin Smith2015-06-14-0/+7
* arm: mvebu: Disable L2 cache before enabling d-cacheStefan Roese2015-06-14-0/+8
* arm: mvebu: Remove "u-boot.kwb" CONFIG_BUILD_TARGET for non-SPL targetsStefan Roese2015-05-05-2/+0
* arm: mvebu: Add d-cache invalidate before enabling the d-cacheStefan Roese2015-05-05-0/+3
* arm: mvebu: Remove coherency configurationStefan Roese2015-05-05-3/+0
* arm: mvebu: Change network init code to allow a more flexible setupStefan Roese2015-05-05-4/+16
* arm: mvebu: Add basic Armada 38x supportStefan Roese2015-05-05-16/+73
* arm: mvebu: Move CONFIG_SPL_LDSCRIPT to common headerStefan Roese2015-05-05-0/+5
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