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* ARM: keystone2: PLL: Enable glitch free initialization sequenceLokesh Vutla2016-11-13-8/+8
| | | | | | | | | | Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone: rename clk_get_rate() to ks_clk_get_rate()Masahiro Yamada2016-10-08-12/+12
| | | | | | | | | | | | | The KeyStone platform has its own clk_get_rate() but its prototype is different from that of the common-clk (clk-uclass) framework. Prefix the KeyStone specific implementation with ks_ in order to avoid name-space conflict. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: K2G: Add support for different arm/device speedsLokesh Vutla2016-03-14-2/+5
| | | | | | | | | | The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Allow for board specific speed definitionsLokesh Vutla2016-03-14-6/+6
| | | | | | | | | | Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific speed definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: k2g: Add clock informationVitaly Andrianov2015-10-22-0/+4
| | | | | | | | Add clock information for Galileo Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: k2g: Add pll dataVitaly Andrianov2015-10-22-0/+5
| | | | | | | Add pll data for k2g Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: k2e/l: Apply WA for selecting PA clock sourceLokesh Vutla2015-10-17-3/+7
| | | | | | | | | | | | | | | On keystone2 Lamarr and Edison platforms, the PA clocksource mux in PLL REG1, can be changed only after enabling its clock domain. So selecting the output of PASS PLL as input to PA only after enabling the clockdomain. This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>" and based on the previous work done by "Hao Zhang <hzhang@ti.com>" Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code") Reported-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Use common definition for clk_get_rateLokesh Vutla2015-08-12-0/+139
| | | | | | | | Since all the clocks are defined common, and has the same logic to get the frequencies, use a common definition for for clk_get_rate(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup init_pll definitionLokesh Vutla2015-08-12-4/+8
| | | | | | | | | This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Use common structure for PLLsLokesh Vutla2015-08-12-0/+8
| | | | | | | | | | Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Fix dev and arm speed detectionLokesh Vutla2015-08-12-25/+38
| | | | | | | | | Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: keystone2: Cleanup PLL init codeLokesh Vutla2015-08-12-166/+135
| | | | | | | | | | | There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* keystone2: use correct EFUSE_BOOTROM fileds to configure speedVitaly Andrianov2015-06-19-6/+6
| | | | | | | | The get_max_arm_speed() and get_max_dev_speed() used wrong register fields to get the maximum speeds. This commit fixes the bug. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone: move SoC sources to mach-keystoneMasahiro Yamada2015-02-21-0/+272
Move arch/arm/cpu/armv7/keystone/* -> arch/arm/mach-keystone/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com>
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