summaryrefslogtreecommitdiff
path: root/arch/arm/lib
Commit message (Collapse)AuthorAgeLines
...
* Change e-mail address of Kamil LulkoKamil Lulko2015-12-05-2/+2
| | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* common: bootm: check return value of strict_strtoulPeng Fan2015-12-05-1/+4
| | | | | | | | | | | | | | Before continue, check return value of strict_strtoul. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-3/+38
| | | | | | | | | | | | When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: fix compile warnings when semihosting is enabled on ARMv7M target.Vadzim Dambrouski2015-11-10-2/+2
| | | | | | | | | | | This patch fixes compile warnings like this: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' In C99 standard you can use %zu modifier to print size_t values. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
* arm: add support for semihosting for ARMv7M targetsVadzim Dambrouski2015-11-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
* arm: Switch 32-bit ARM to using generic global_data setupSimon Glass2015-10-24-24/+4
| | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Switch aarch64 to using generic global_data setupSimon Glass2015-10-24-12/+3
| | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Tested on LS2085ARDB and LS2085AQDS (armv8 SoC). Tested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* armv8/gic: Fix GIC v2 initializationThierry Reding2015-10-15-1/+9
| | | | | | | | | | | | | Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2015-10-14-690/+0
|\
| * arm: Drop old non-generic-board codeSimon Glass2015-09-28-690/+0
| | | | | | | | | | | | | | This code is no-longer used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
* | arm: Correct comments in crt0.S for the recent SPL improvementsSimon Glass2015-09-12-20/+36
|/ | | | | | | | | | The current comments need a bit of tweaking since we now support stack and global_data relocation in SPL. Also add a reference to the README. For AArch64 this is not implemented, so leave a TODO for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tim Harvey <tharvey@gateworks.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-0/+2
|\
| * arm: reset: Avoid a build error when the reset uclass is enabledSimon Glass2015-09-02-0/+2
| | | | | | | | | | | | | | There can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | armv8: Add framework for CCN-504 interconnect configurationBhupesh Sharma2015-09-01-0/+62
|/ | | | | | | | | | | | This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-12-2/+2
| | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-21/+5
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-0/+9
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-2/+2
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-07-17/+30
| | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
* common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()Matt Porter2015-05-28-0/+45
| | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Signed-off-by: Matt Porter <mporter@konsulko.com>
* arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>Tom Rini2015-05-14-0/+2
| | | | | | | | | With d6b72da0 we started including this file unconditionally. This isn't allowed in a file that we also use on armv8. This will get cleaned up a bit better once we really start using these same features (and have similar fdt updates needed) on armv8. Signed-off-by: Tom Rini <trini@konsulko.com>
* virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-13-0/+6
| | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-4/+4
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-05-05-3/+210
|\
| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-0/+7
| |\
| | * armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARM: Add ARMv7-M supportrev13@wp.pl2015-04-22-2/+201
| |/ | | | | | | Signed-off-by: Kamil Lulko <rev13@wp.pl>
| * net: Remove the bd* parameter from net stack functionsJoe Hershberger2015-04-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This value is not used by the network stack and is available in the global data, so stop passing it around. For the one legacy function that still expects it (init op on old Ethernet drivers) pass in the global pointer version directly to avoid changing that interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
| * common: Make sure arch-specific map_sysmem() is definedJoe Hershberger2015-04-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko2015-04-16-0/+14
|/ | | | | | | | The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-2/+11
|\ | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-2/+11
| | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | armv8: semihosting: delete external interfaceLinus Walleij2015-03-28-92/+0
| | | | | | | | | | | | | | | | | | | | | | Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: add a command to load semihosted imagesLinus Walleij2015-03-28-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: do not inline trap callLinus Walleij2015-03-28-1/+1
|/ | | | | | | | The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-4/+9
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-02-24-0/+43
| |\
| * | arm: Show relocated PC/LR in the register dumpSimon Glass2015-02-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
* | | arm: relocation: clear .bss section with arch memset if definedPrzemyslaw Marczak2015-03-09-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1384ms - before this change - ~888ms - after this change Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | arm: spl: Allow board_init_r() to run with a larger stackSimon Glass2015-03-04-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SPL uses a single stack, either CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and environment) require a lot of stack, some boards set CONFIG_SPL_STACK to point into SDRAM. They then set up SDRAM very early, before board_init_f(), so that the larger stack can be used. This is an abuse of lowlevel_init(). That function should only be used for essential start-up code which cannot be delayed. An example of a valid use is when only part of the SPL code is visible/executable, and the SoC must be set up so that board_init_f() can be reached. It should not be used for SDRAM init, console init, etc. Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new address before board_init_r() is called in SPL. The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README. Signed-off-by: Simon Glass <sjg@chromium.org> For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: spl: Avoid setting up a duplicate global data structureSimon Glass2015-03-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is already set up in crt0.S. We don't need a new structure and don't really want one in the 'data' section of the image, since it will be empty and crt0.S's changes will be ignored. As an interim measure, remove it only if CONFIG_DM is not defined. This allows us to press ahead with driver model in SPL and allow the stragglers to catch up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-1/+1
|\ \ \
| * | | armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
* | | ARM: remove jadecpu board supportMasahiro Yamada2015-02-24-46/+0
|/ / | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>
* | common/board_f: factor out reserve_stacksAndreas Bießmann2015-02-17-0/+43
|/ | | | | | | | Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to the architecture needs. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-0/+2
|\
| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | arm: Add warnings about using gdataSimon Glass2015-01-16-1/+6
|/ | | | | | | | | We need to get rid of this SPL-specific setting of the global_data pointer. It is already set up in start.S immediately before board_init_f() is called, and there may be information there that is needed (e.g. pre-reloc malloc info). Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-08 00:37:01 +0000