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* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2017-04-05-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82) (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795) (cherry picked from commit 2b29c1873c2293abe1c4b361392521223b9c9ecf)
* do_smhload: fix return codeRyan Harkin2017-03-09-2/+2
| | | | | | | | | | | | | do_smhload was using a ulong to store the return value from smh_load_file. That returns an int, where -1 indicates an error. As a ulong will never be negative, smh_load_file errors were not detected and so_smhload always returned zero. Also, when errors were spotted, do_smhload was returning 1, rather than the enumeration CMD_RET_FAILURE (which is also 1). Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* armv8: spl: Call spl_relocate_stack_gd for ARMv8Philipp Tomsich2017-03-01-2/+12
| | | | | | | | | | As part of the startup process for boards using the SPL, we need to call spl_relocate_stack_gd. This is needed to set up malloc with its DRAM buffer. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: fix comment in relocate_64.SMasahiro Yamada2017-02-08-1/+1
| | | | | | | | | | | | | There are two typos in the comment "invalide i-cache is enabled". We can fix it by invalide -> invalidate is -> if Or, if we want to match the comment to the code, we can say "skip invalidating i-cache if disabled". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: use store with auto-incrementMasahiro Yamada2017-02-08-2/+1
| | | | | | | Save one instruction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: use xzr to zero-out the bss sectionMasahiro Yamada2017-02-08-2/+1
| | | | | | | AArch64 has a zero register (xzr). Use it instead of x2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: Default to using optimized memset and memcpy routinesTom Rini2017-01-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | We have long had available optimized versions of the memset and memcpy functions that are borrowed from the Linux kernel. We should use these in normal conditions as the speed wins in many workflows outweigh the relatively minor size increase. However, we have a number of places where we're simply too close to size limits in SPL and must be able to make the size vs performance trade-off in those cases. Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: Heiko Schocher <hs@denx.de> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-7/+7
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| * ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCIHou Zhiqiang2017-01-18-2/+2
| | | | | | | | | | | | | | | | Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: aarch64: Fix the warning about x1-x3 nonzero issueAlison Wang2017-01-18-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARM: boot0 hook: remove macro, include whole header fileAndre Przywara2017-01-04-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For prepending some board specific header area to U-Boot images we were so far including a header file with a macro definition containing the actual header specification. This works fine if there are just a few statements and if there is only one alternative. However adding more complex code quickly gets messy with this approach, so let's just drop that intermediate macro and let the #include actually insert the code directly. This converts the callers and the callees, but doesn't change anything at this point. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | armv8: prevent using THUMBAndre Przywara2017-01-04-0/+2
|/ | | | | | | | | | | | | | | | The predominantely 32-bit ARM targets try to compile the SPL in Thumb mode to reduce code size. The 64-bit AArch64 instruction set does not know an alternative, concise encoding, so the Thumb build option should only be set for 32-bit targets. Likewise -marm machine options are only valid for ARMv7 targets. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-3/+8
| | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-2/+2
| | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORYMasahiro Yamada2016-12-02-4/+0
| | | | | | | | | | | | | | | | | | Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option") allows us to skip memory setup of DTB, but a problem for ARM is that spin_table_update_dt() and psci_update_dt() are skipped as well if CONFIG_ARCH_FIXUP_FDT is disabled. This commit allows us to skip only fdt_fixup_memory_banks() instead of the whole of arch_fixup_fdt(). It will be useful when we want to use a memory node from a kernel DTB as is, but need some fixups for Spin-Table/PSCI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for x86: Signed-off-by: Simon Glass <sjg@chromium.org>
* efi_loader: Allow to compile helloworld.efi w/o bundling itAlexander Graf2016-11-27-1/+1
| | | | | | | | | | | | | | | | | Today we can compile a self-contained hello world efi test binary that allows us to quickly verify whether the EFI loader framwork works. We can use that binary outside of the self-contained test case though, by providing it to a to-be-tested system via tftp. This patch separates compilation of the helloworld.efi file from including it in the u-boot binary for "bootefi hello". It also modifies the efi_loader test case to enable travis to pick up the compiled file. Because we're now no longer bloating the resulting u-boot binary, we can enable compilation always, giving us good travis test coverage. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+6
| | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-5/+34
| | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-0/+7
| | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
* efi: arm: Add aarch64 EFI app supportSimon Glass2016-11-14-0/+292
| | | | | | | | | Add support for EFI apps on aarch64. This includes start-up and relocation code plus a link script. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
* efi: arm: Add EFI app supportSimon Glass2016-11-14-0/+284
| | | | | | | | | Add support for EFI apps on ARM. This includes start-up and relocation code, plus a link script and some compiler setting changes. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Remove whitespace change, add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
* elf: arm: Add a few ARM relocation typesSimon Glass2016-11-14-2/+4
| | | | | | | | Rather than hard-coding the relocation type, add it to the ELF header file and use it from there. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-0/+5
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* spl: Add a parameter to jump_to_image_linux()Simon Glass2016-10-06-2/+2
| | | | | | | | Instead of using the global spl_image variable, pass the required struct in as an argument. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: cache: always flush cache line size for page tableStefan Agner2016-08-26-1/+13
| | | | | | | | | | | | The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* arm: cache: add support for LPAE for region D$ behaviorStefan Agner2016-08-26-0/+4
| | | | | | | Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini2016-08-26-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* cmd: Split 'bootz' and 'booti' out from 'bootm'Tom Rini2016-08-20-1/+2
| | | | | | | | | | | | The bootz and booti commands rely on common functionality that is found in common/bootm.c and common/bootm_os.c. They do not however rely on the rest of cmd/bootm.c to be implemented so split them into their own files. Have various Makefiles include the required infrastructure for CONFIG_CMD_BOOT[IZ] as well as CONFIG_CMD_BOOTM. Move the declaration of 'images' over to common/bootm.c. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* vexpress: Check TC2 firmware support before defaulting to nonsec bootingJon Medhurst \(Tixy\)2016-08-15-5/+10
| | | | | | | | | | The firmware on TC2 needs to be configured appropriately before booting in nonsec mode will work as expected, so test for this and fall back to sec mode if required. Signed-off-by: Jon Medhurst <tixy@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ARM: Rework and correct barrier definitionsTom Rini2016-08-05-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-08-02-43/+37
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| * arm/PSCI: Add support for creating ARMv7 PSCI version 1.0 DT nodeHou Zhiqiang2016-08-02-0/+2
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Fixed the backward compatiblity issueHou Zhiqiang2016-08-02-26/+35
| | | | | | | | | | | | | | | | | | | | | | | | Appended the compatible strings of old version PSCI to the latest version supported. And there are some psci functions' property must be added to DT only for psci version 0.1, including cpu_on, cpu_off, cpu_suspend, migrate. Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm/PSCI: Removed unused codeHou Zhiqiang2016-08-02-17/+0
| | | | | | | | | | | | | | | | Identify the PSCI node only by its name, so removed the code finding it by compatible string. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | libfdt: Introduce new ARCH_FIXUP_FDT optionMichal Simek2016-07-31-0/+4
|/ | | | | | | | | | Add new Kconfig option to disable arch_fixup_fdt() calls for cases where U-Boot shouldn't update memory setup in DTB file. One example of usage of this option is to boot OS with different memory setup than U-Boot use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
* armv8: spl: Call board_init_r from crt0_64 in SPLJeremy Hunt2016-07-22-15/+12
| | | | | | | | | | | | | | | As part of the startup process for boards using the SPL, the meaning of board_init_f changed such that it should return normally rather than calling board_init_r directly. (see db910353a126d84fe8dff7a694ea792f50fcfb6a ) This was fixed in 32-bit arm, but broke when SPL was added to 64 bit arm. This fixes crt0_64 so that it calls board_init_r during the SPL and removes the direct call from board_init_f from the arm SPL example. Signed-off-by: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com> Acked-by: Simon Glass <sjg@chromium.org>
* spl: zImage support in Falcon modeLadislav Michl2016-07-22-32/+42
| | | | | | | | Other payload than uImage is currently considered to be raw U-Boot image. Check also for zImage in Falcon mode. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* spl: Fix compilation warnings for arm64Michal Simek2016-07-22-1/+1
| | | | | | | | | | | | | | | Make code 64bit aware. Warnings: +../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’: +../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +../common/spl/spl_fat.c: In function ‘spl_load_image_fat’: +../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-1/+126
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * ARMv8/PSCI: Fixup the device tree for PSCIHou Zhiqiang2016-07-19-1/+126
| | | | | | | | | | | | | | | | Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-0/+2
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| * | ARM: Add an empty secure stack sectionChen-Yu Tsai2016-07-15-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now we've been using memory beyond psci_text_end as stack space for the secure monitor or PSCI implementation, even if space was not allocated for it. This was partially fixed in ("ARM: allocate extra space for PSCI stack in secure section during link phase"). However, calculating stack space from psci_text_end in one place, while allocating the space in another is error prone. This patch adds a separate empty secure stack section, with space for CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also __secure_stack_start and __secure_stack_end symbols. The linker script handles calculating the correct VMAs for the stack section. For platforms that relocate/copy the secure monitor before using it, the space is not allocated in the executable, saving space. For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page of stack space for 4 CPUs is allocated, matching the previous behavior. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | arm: Show cache warnings in U-Boot proper onlySimon Glass2016-07-14-2/+2
| | | | | | | | | | | | Avoid bloating the SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move check_cache_range() into a common placeSimon Glass2016-07-14-0/+22
| | | | | | | | | | | | | | This code is common, so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | arm64: add better and more generic spin-table supportMasahiro Yamada2016-07-14-0/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: move #ifdef to match the error handling codeMasahiro Yamada2016-06-24-2/+5
| | | | | | | | | | | | Match the #ifdef ... #endif and the code, ret = do_something(); if (ret) return ret; This will make it easier to add more #ifdef'ed code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm/arm64: implement a boot header capabilityAndre Przywara2016-06-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0) require a header before the actual U-Boot binary to both check its validity and to find other data to load. Sometimes this header may only be a few bytes of information, and sometimes this might simply be space that needs to be reserved for a post-processing tool. Introduce a config option to allow assembler preprocessor commands to be inserted into the code at the appropriate location; typical assembler preprocessor commands might be: .space 1000 .word 0x12345678 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Steve Rae <srae@broadcom.com> Commit Notes: Please note that the current code: start.S (arm64) and vectors.S (arm) already jumps over some portion of data already, so this option basically just increases the size of this region (and the resulting binary). For use with Allwinner's boot0 blob there is a tool called boot0img[1], which fills the header to allow booting A64 based boards. For the Pine64 we need a 1536 byte header (including the branch instruction) at the moment, so we add this to the defconfig. [1] https://github.com/apritzel/pine64/tree/master/tools END Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Fix fix push/pop-section directivesMarek Vasut2016-06-04-2/+2
| | | | | | | | | | | | Repair typos in the previous "arm: lib: fix push/pop-section directives" patch, which prevented VCMA9 board from building. Signed-off-by: Marek Vasut <marex@denx.de> Fixes: b2f1858455e9 ("arm: lib: fix push/pop-section directives") Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stephen Warren <swarren@nvidia.com>
* arm: lib: fix push/pop-section directivesStephen Warren2016-06-03-34/+34
| | | | | | | | | | | | | | | | | | | | | | | With the existing code, function symbols are defined in .text, and the body is defined in .text.xxx. This causes (at least some version of) the linker not to emit the function body into the final binary, since it's part of a different section to the symbols being referenced. This of course causes a wide variety of failures. This change moves the push/pop-section directives before the function symbols, and after any relate ENDPROC macro invocations, so that symbols and bodies are all in the "pushed" sections, and thus the function bodies are emitted into the binary. This solves (at least) the boot problems currently seen on Tegra systems that use SPL (i.e. all ARMv7 Tegras). Fixes: 13b0a91a6d48 ("arm: lib: Split asm symbols into different .text subsections") Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-11-01 11:25:19 +0000