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* ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-12-2/+2
| | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-21/+5
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-0/+9
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-2/+2
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-07-17/+30
| | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
* common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()Matt Porter2015-05-28-0/+45
| | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Signed-off-by: Matt Porter <mporter@konsulko.com>
* arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>Tom Rini2015-05-14-0/+2
| | | | | | | | | With d6b72da0 we started including this file unconditionally. This isn't allowed in a file that we also use on armv8. This will get cleaned up a bit better once we really start using these same features (and have similar fdt updates needed) on armv8. Signed-off-by: Tom Rini <trini@konsulko.com>
* virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-13-0/+6
| | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-4/+4
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-05-05-3/+210
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| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-0/+7
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| | * armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARM: Add ARMv7-M supportrev13@wp.pl2015-04-22-2/+201
| |/ | | | | | | Signed-off-by: Kamil Lulko <rev13@wp.pl>
| * net: Remove the bd* parameter from net stack functionsJoe Hershberger2015-04-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This value is not used by the network stack and is available in the global data, so stop passing it around. For the one legacy function that still expects it (init op on old Ethernet drivers) pass in the global pointer version directly to avoid changing that interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
| * common: Make sure arch-specific map_sysmem() is definedJoe Hershberger2015-04-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko2015-04-16-0/+14
|/ | | | | | | | The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-2/+11
|\ | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-2/+11
| | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | armv8: semihosting: delete external interfaceLinus Walleij2015-03-28-92/+0
| | | | | | | | | | | | | | | | | | | | | | Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: add a command to load semihosted imagesLinus Walleij2015-03-28-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: do not inline trap callLinus Walleij2015-03-28-1/+1
|/ | | | | | | | The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-4/+9
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-02-24-0/+43
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| * | arm: Show relocated PC/LR in the register dumpSimon Glass2015-02-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
* | | arm: relocation: clear .bss section with arch memset if definedPrzemyslaw Marczak2015-03-09-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1384ms - before this change - ~888ms - after this change Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | arm: spl: Allow board_init_r() to run with a larger stackSimon Glass2015-03-04-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SPL uses a single stack, either CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and environment) require a lot of stack, some boards set CONFIG_SPL_STACK to point into SDRAM. They then set up SDRAM very early, before board_init_f(), so that the larger stack can be used. This is an abuse of lowlevel_init(). That function should only be used for essential start-up code which cannot be delayed. An example of a valid use is when only part of the SPL code is visible/executable, and the SoC must be set up so that board_init_f() can be reached. It should not be used for SDRAM init, console init, etc. Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new address before board_init_r() is called in SPL. The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README. Signed-off-by: Simon Glass <sjg@chromium.org> For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: spl: Avoid setting up a duplicate global data structureSimon Glass2015-03-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is already set up in crt0.S. We don't need a new structure and don't really want one in the 'data' section of the image, since it will be empty and crt0.S's changes will be ignored. As an interim measure, remove it only if CONFIG_DM is not defined. This allows us to press ahead with driver model in SPL and allow the stragglers to catch up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-1/+1
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| * | | armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
* | | ARM: remove jadecpu board supportMasahiro Yamada2015-02-24-46/+0
|/ / | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>
* | common/board_f: factor out reserve_stacksAndreas Bießmann2015-02-17-0/+43
|/ | | | | | | | Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to the architecture needs. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-0/+2
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| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | arm: Add warnings about using gdataSimon Glass2015-01-16-1/+6
|/ | | | | | | | | We need to get rid of this SPL-specific setting of the global_data pointer. It is already set up in start.S immediately before board_init_f() is called, and there may be information there that is needed (e.g. pre-reloc malloc info). Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: build arch memset/memcpy in Thumb2 modeStefan Agner2015-01-09-81/+111
| | | | | | | | | | | | | | | | | | | | | | Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
* ARM: bootm: do not add PSCI to fdt when booting in secure mode.Ian Campbell2015-01-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8bc347e2ec17 "ARM: bootm: Allow booting in secure mode on hyp capable systems" added the capability to select nonsec vs sec mode boot via an environment var. There is a subtle gotcha with this functionality, which is that the PSCI nodes are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting in secure mode. Which means that if the kernel is PSCI aware then it will fail to boot because it will try and do PSCI from secure world, which won't work. This likely didn't get noticed before because the original purpose was to support booting the legacy linux-sunxi kernels which don't understand PSCI. To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and use from the virt-dt code. As well as avoiding the creation of the PSCI nodes we should also avoid reserving the secure RAM, so do so. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-0/+44
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| * ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: semihosting: get rid of forward declarationsLinus Walleij2014-12-29-89/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By rearranging the functions in the semihosting code we can avoid forward-declaration of the internal static functions. This puts the stuff in a logical order: read/open/close/len and then higher-order functions follow at the end. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | arm: semihosting: fix up compile bugsLinus Walleij2014-12-29-49/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is currently a regression when using newer ARM64 compilers for semihosting: the way long types are inferred from context is no longer the same. The semihosting runtime uses long and size_t, so use this explicitly in the semihosting code and interface, and voila: the code now works again. Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | arm: semihosting: staticize internal functionsLinus Walleij2014-12-29-4/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | The semihosting code exposes internal file handle handling functions to read(), open(), close() and get the length of a certain file handle. However the code using it is only interested in either reading and entire named file into memory or getting the file length of a file referred by name. No file handles are used. Thus make the file handle code internal to this file by removing these functions from the semihosting header file and staticize them. This gives us some freedom to rearrange the semihosting code without affecting the external interface. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-24-5/+26
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| * ARM: bootm: Allow booting in secure mode on hyp capable systemsHans de Goede2014-11-24-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older Linux kernels will not properly boot in hyp mode, add support for a bootm_boot_mode environment variable, which can be set to "sec" or "nonsec" to force booting in secure or non-secure mode when build with non-sec support. The default behavior can be selected through CONFIG_ARMV7_BOOT_SEC_DEFAULT, when this is set booting in secure mode is the default. The default setting for this Kconfig option is N, preserving the current behavior of booting in non-secure mode by default when non-secure mode is supported. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-30/+48
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| * | imx: fix exception vectors relocation in imx27Albert ARIBAUD2014-11-20-28/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff46cc4 fixed exception vectors setting in the general ARM case, by either copying the exception and indirect vector tables to normal (0x00000000) or high (0xFFFF0000) vectors address, or setting VBAR to U-Boot's base if applicable. i.MX27 SoC is ARM926E-JS, thus has only normal and high options, but does not provide RAM at 0xFFFF0000 and has only ROM at 0x00000000; it is therefore not possible to move or change its exception vectors. Besides, i.MX27 ROM code does provide an indirect vectors table but at a non-standard address and with the reset and reserved vectors missing. Turn the current vector relocation code into a weak routine called after relocate_code from crt0, and add strong version for i.MX27. Series-Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Tested-by: Philippe Reynes <tremyfr@gmail.com> Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
| * | cosmetic: arm: fix whitespace in arch/arm/lib/relocate.SAlbert ARIBAUD2014-11-20-4/+4
| |/ | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-1/+1
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | dm: arm: spl: Allow simple malloc() in SPLSimon Glass2014-11-21-1/+1
| |/ | | | | | | | | | | | | | | For SPL it is sometimes useful to have a simple malloc() just to permit driver model to work, in the cases where the full malloc() is not made available by the board config. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-14 20:18:43 +0000