summaryrefslogtreecommitdiff
path: root/arch/arm/lib
Commit message (Collapse)AuthorAgeLines
* arm: Add a 64-bit division routine to the private librarySimon Glass2016-03-17-1/+247
| | | | | | | | | | | | This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+8
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, r9 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+9
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, x18 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: Add runtime servicesAlexander Graf2016-03-15-0/+4
| | | | | | | | | | | | | | | | | After booting has finished, EFI allows firmware to still interact with the OS using the "runtime services". These callbacks live in a separate address space, since they are available long after U-Boot has been overwritten by the OS. This patch adds enough framework for arbitrary code inside of U-Boot to become a runtime service with the right section attributes set. For now, we don't make use of it yet though. We could maybe in the future map U-boot environment variables to EFI variables here. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm: make sure board_init_r() is being called using the right mode (ARM / THUMB)David Müller (ELSOFT AG)2016-02-15-1/+5
| | | | Signed-off-by: David Müller <d.mueller@elsoft.ch>
* arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7Marek Vasut2016-01-31-1/+1
| | | | | | | | | | | | | | | | | | | | | The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* ARM: bootm: Try to use relocated ramdiskJeffy Chen2016-01-21-1/+11
| | | | | | | | | After boot_ramdisk_high(), ramdisk would be relocated to initrd_start & initrd_end, so use them instead of rd_start & rd_end. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: initialize gd for AArch64Stephen Warren2016-01-14-0/+2
| | | | | | | | | | | Commit adc421e4cee8 "arm: move gd handling outside of C code" removed the call to arch_setup_gd() on ARM and replaced it with assembly code in crt0.S. However, AArch64 uses a different startup file, and the same change was not made to it. This leaves gd uninitialized on AArch64, which typically leads to hangs or crashes. This change fixes that. Fixes: adc421e4cee8 ("arm: move gd handling outside of C code") Signed-off-by: Stephen Warren <swarren@nvidia.com>
* arm: move gd handling outside of C codeAlbert ARIBAUD2016-01-13-0/+3
| | | | | | | | | | | | | | | | | | As of gcc 5.2.1 for Thumb-1, it is not possible any more to assign gd from C code, as gd is mapped to r9, and r9 may now be saved in the prolog sequence, and restored in the epilog sequence, of any C functions. Therefore arch_setup_gd(), which is supposed to set r9, may actually have no effect, causing U-Boot to use a bad address to access GD. Fix this by never calling arch_setup_gd() for ARM, and instead setting r9 in arch/arm/lib/crt0.S, to the value returned by board_init_f_alloc_reserve(). Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix board init code to respect the C runtime environmentAlbert ARIBAUD2016-01-13-2/+5
| | | | | | | | | | | | | board_init_f_mem() alters the C runtime environment's stack it is actually already using. This is not a valid behaviour within a C runtime environment. Split board_init_f_mem into C functions which do not alter their own stack and always behave properly with respect to their C runtime environment. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Thomas Chou <thomas@wytron.com.tw>
* Change e-mail address of Kamil LulkoKamil Lulko2015-12-05-2/+2
| | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* common: bootm: check return value of strict_strtoulPeng Fan2015-12-05-1/+4
| | | | | | | | | | | | | | Before continue, check return value of strict_strtoul. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: support Thumb-1 with CONFIG_SYS_THUMB_BUILDAlbert ARIBAUD2015-11-10-3/+38
| | | | | | | | | | | | When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD, some files fail to build, most of the time because they include mcr instructions, which only exist for Thumb-2. This patch introduces a Kconfig option CONFIG_THUMB2 and uses it to select between Thumb-2 and ARM mode for the aforementioned files. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: fix compile warnings when semihosting is enabled on ARMv7M target.Vadzim Dambrouski2015-11-10-2/+2
| | | | | | | | | | | This patch fixes compile warnings like this: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' In C99 standard you can use %zu modifier to print size_t values. Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
* arm: add support for semihosting for ARMv7M targetsVadzim Dambrouski2015-11-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | If you enable CONFIG_SEMIHOSTING for STM32F429 target, you will get compile error looking like this: arch/arm/lib/semihosting.c: In function 'smh_read': {standard input}: Assembler messages: {standard input}:34: Error: invalid swi expression {standard input}:34: Error: value of 1193046 too large for field of 2 bytes at 0 scripts/Makefile.build:277: recipe for target 'arch/arm/lib/semihosting.o' failed The source of the problem is "svc #0x123456" instruction. This instruction can not be encoded using Thumb2 instruction set used by ARMv7M CPUs. ARM documentation suggests using "bkpt #0xAB" instruction instead [1]. This patch fixes compile errors and adds support for semihosting for STM32F429 or any other ARMv7M target. This change was sested on STM32F429-DISCOVERY board using OpenOCD and "smhload" u-boot command. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/Bgbjhiea.html Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
* arm: Switch 32-bit ARM to using generic global_data setupSimon Glass2015-10-24-24/+4
| | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Switch aarch64 to using generic global_data setupSimon Glass2015-10-24-12/+3
| | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Tested on LS2085ARDB and LS2085AQDS (armv8 SoC). Tested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* armv8/gic: Fix GIC v2 initializationThierry Reding2015-10-15-1/+9
| | | | | | | | | | | | | Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable interrupts to the primary CPU. This fixes issues seen after booting a Linux kernel from U-Boot. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2015-10-14-690/+0
|\
| * arm: Drop old non-generic-board codeSimon Glass2015-09-28-690/+0
| | | | | | | | | | | | | | This code is no-longer used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
* | arm: Correct comments in crt0.S for the recent SPL improvementsSimon Glass2015-09-12-20/+36
|/ | | | | | | | | | The current comments need a bit of tweaking since we now support stack and global_data relocation in SPL. Also add a reference to the README. For AArch64 this is not implemented, so leave a TODO for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tim Harvey <tharvey@gateworks.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-0/+2
|\
| * arm: reset: Avoid a build error when the reset uclass is enabledSimon Glass2015-09-02-0/+2
| | | | | | | | | | | | | | There can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | armv8: Add framework for CCN-504 interconnect configurationBhupesh Sharma2015-09-01-0/+62
|/ | | | | | | | | | | | This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-12-2/+2
| | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-21/+5
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-0/+9
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* spl, common, serial: build SPL without serial supportHeiko Schocher2015-08-12-2/+2
| | | | | | | | | This patch enables building SPL without CONFIG_SPL_SERIAL_SUPPORT support. Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Ensure we build arch/arm/imx-common on mx28] Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-07-17/+30
| | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
* common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()Matt Porter2015-05-28-0/+45
| | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Signed-off-by: Matt Porter <mporter@konsulko.com>
* arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>Tom Rini2015-05-14-0/+2
| | | | | | | | | With d6b72da0 we started including this file unconditionally. This isn't allowed in a file that we also use on armv8. This will get cleaned up a bit better once we really start using these same features (and have similar fdt updates needed) on armv8. Signed-off-by: Tom Rini <trini@konsulko.com>
* virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-13-0/+6
| | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-4/+4
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-05-05-3/+210
|\
| * Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-0/+7
| |\
| | * armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | ARM: Add ARMv7-M supportrev13@wp.pl2015-04-22-2/+201
| |/ | | | | | | Signed-off-by: Kamil Lulko <rev13@wp.pl>
| * net: Remove the bd* parameter from net stack functionsJoe Hershberger2015-04-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This value is not used by the network stack and is available in the global data, so stop passing it around. For the one legacy function that still expects it (init op on old Ethernet drivers) pass in the global pointer version directly to avoid changing that interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
| * common: Make sure arch-specific map_sysmem() is definedJoe Hershberger2015-04-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko2015-04-16-0/+14
|/ | | | | | | | The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-2/+11
|\ | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-2/+11
| | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | armv8: semihosting: delete external interfaceLinus Walleij2015-03-28-92/+0
| | | | | | | | | | | | | | | | | | | | | | Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: add a command to load semihosted imagesLinus Walleij2015-03-28-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: do not inline trap callLinus Walleij2015-03-28-1/+1
|/ | | | | | | | The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-4/+9
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-02-24-0/+43
| |\
| * | arm: Show relocated PC/LR in the register dumpSimon Glass2015-02-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-12-22 08:19:20 +0000