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* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
* MLK-10774-33 imx:mx6 add udc and fastboot supportPeng Fan2015-04-29-0/+12
| | | | | | | | | | | | Add udc and fastboot support We did not use the upstream way. Currently use CI_UDC and USB_GAGDET of upstream can make fastboot work, but lack of flash operation, so we still use our way. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-04-03-2/+11
|\ | | | | | | | | | | | | Conflicts: board/armltd/vexpress64/vexpress64.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARMv8: enable pre-allocation mallocDavid Feng2015-03-27-2/+11
| | | | | | | | | | | | | | Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | armv8: semihosting: delete external interfaceLinus Walleij2015-03-28-92/+0
| | | | | | | | | | | | | | | | | | | | | | Now that loading files using semihosting can be done using a command in standard scripts, and we have rewritten the boardfile and added it to the Vexpress64, let's delete the external interface to the semihosting file retrieveal and rely solely on these commands, and staticize them inside that file so the whole business is self-contained. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: add a command to load semihosted imagesLinus Walleij2015-03-28-0/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of sprinkling custom code and calls over the Vexpress64 boardfile, create a command that loads images using semihosting just like we would load from flash memory of over the network, using a special command: smhload <image> <address> This will make it possible to remove some custom calls and code and make the boot easier. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | armv8: semihosting: do not inline trap callLinus Walleij2015-03-28-1/+1
|/ | | | | | | | The semihosting trap call does not like being inlined, probably because that will mean register reordering screwing up the return value in r0, so tag this function "noinline". Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-4/+9
|\ | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-02-24-0/+43
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| * | arm: Show relocated PC/LR in the register dumpSimon Glass2015-02-03-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't know the relocation address, the raw values are not very useful. Show the pre-relocation values as well as these can be looked up in System.map, etc. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: PSCI: Rework the DT handler slightlyTom Rini2015-03-09-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way the PSCI DT update happens currently means we pull in <asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in <asm/io.h> for some non-PSCI related things that header needs to deal with. To fix this, we rework the hook slightly. A good portion of arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI is needed on ARMv8 we can re-use this by and large. So rename the current hook to psci_update_dt(), move the prototype to <asm/psci.h> and add an #ifdef that will make re-use later easier. Reported-by: York Sun <yorksun@freescale.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: York Sun <yorksun@freescale.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: York Sun <yorksun@freescale.com>
* | | arm: relocation: clear .bss section with arch memset if definedPrzemyslaw Marczak2015-03-09-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. This was tested on Trats2. A quick test with trace. Boot time from start to main_loop() entry: - ~1384ms - before this change - ~888ms - after this change Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | arm: spl: Allow board_init_r() to run with a larger stackSimon Glass2015-03-04-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present SPL uses a single stack, either CONFIG_SPL_STACK or CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and environment) require a lot of stack, some boards set CONFIG_SPL_STACK to point into SDRAM. They then set up SDRAM very early, before board_init_f(), so that the larger stack can be used. This is an abuse of lowlevel_init(). That function should only be used for essential start-up code which cannot be delayed. An example of a valid use is when only part of the SPL code is visible/executable, and the SoC must be set up so that board_init_f() can be reached. It should not be used for SDRAM init, console init, etc. Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new address before board_init_r() is called in SPL. The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README. Signed-off-by: Simon Glass <sjg@chromium.org> For version 1: Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: spl: Avoid setting up a duplicate global data structureSimon Glass2015-03-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is already set up in crt0.S. We don't need a new structure and don't really want one in the 'data' section of the image, since it will be empty and crt0.S's changes will be ignored. As an interim measure, remove it only if CONFIG_DM is not defined. This allows us to press ahead with driver model in SPL and allow the stragglers to catch up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-1/+1
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| * | | armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stackYork Sun2015-02-24-1/+1
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun <yorksun@freescale.com>
* | | ARM: remove jadecpu board supportMasahiro Yamada2015-02-24-46/+0
|/ / | | | | | | | | | | | | | | This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>
* | common/board_f: factor out reserve_stacksAndreas Bießmann2015-02-17-0/+43
|/ | | | | | | | Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to the architecture needs. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-0/+2
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| * arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | arm: Add warnings about using gdataSimon Glass2015-01-16-1/+6
|/ | | | | | | | | We need to get rid of this SPL-specific setting of the global_data pointer. It is already set up in start.S immediately before board_init_f() is called, and there may be information there that is needed (e.g. pre-reloc malloc info). Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: build arch memset/memcpy in Thumb2 modeStefan Agner2015-01-09-81/+111
| | | | | | | | | | | | | | | | | | | | | | Resynchronize memcpy/memset with kernel 3.17 and build them in Thumb2 mode (unified syntax). Those assembler files can be built and linked in ARM mode too, however when calling them from Thumb2 built code, the stack got corrupted and the copy did not succeed (the exact details have not been traced back). However, the Linux kernel builds those files in Thumb2 mode. Hence U-Boot should build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set. To build the files without warning, some assembler instructions had to be replaced with their UAL compliant variant (thanks Jeroen for this input). To build the file in Thumb2 mode the implicit-it=always option need to be set to generate Thumb2 compliant IT instructions where needed. We add this option to the general AFLAGS when building for Thumb2. Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Agner <stefan@agner.ch>
* ARM: bootm: do not add PSCI to fdt when booting in secure mode.Ian Campbell2015-01-05-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8bc347e2ec17 "ARM: bootm: Allow booting in secure mode on hyp capable systems" added the capability to select nonsec vs sec mode boot via an environment var. There is a subtle gotcha with this functionality, which is that the PSCI nodes are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting in secure mode. Which means that if the kernel is PSCI aware then it will fail to boot because it will try and do PSCI from secure world, which won't work. This likely didn't get noticed before because the original purpose was to support booting the legacy linux-sunxi kernels which don't understand PSCI. To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and use from the virt-dt code. As well as avoiding the creation of the PSCI nodes we should also avoid reserving the secure RAM, so do so. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-01-01-0/+44
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| * ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: semihosting: get rid of forward declarationsLinus Walleij2014-12-29-89/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | By rearranging the functions in the semihosting code we can avoid forward-declaration of the internal static functions. This puts the stuff in a logical order: read/open/close/len and then higher-order functions follow at the end. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | arm: semihosting: fix up compile bugsLinus Walleij2014-12-29-49/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is currently a regression when using newer ARM64 compilers for semihosting: the way long types are inferred from context is no longer the same. The semihosting runtime uses long and size_t, so use this explicitly in the semihosting code and interface, and voila: the code now works again. Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | arm: semihosting: staticize internal functionsLinus Walleij2014-12-29-4/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | The semihosting code exposes internal file handle handling functions to read(), open(), close() and get the length of a certain file handle. However the code using it is only interested in either reading and entire named file into memory or getting the file length of a file referred by name. No file handles are used. Thus make the file handle code internal to this file by removing these functions from the semihosting header file and staticize them. This gives us some freedom to rearrange the semihosting code without affecting the external interface. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-24-5/+26
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| * ARM: bootm: Allow booting in secure mode on hyp capable systemsHans de Goede2014-11-24-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Older Linux kernels will not properly boot in hyp mode, add support for a bootm_boot_mode environment variable, which can be set to "sec" or "nonsec" to force booting in secure or non-secure mode when build with non-sec support. The default behavior can be selected through CONFIG_ARMV7_BOOT_SEC_DEFAULT, when this is set booting in secure mode is the default. The default setting for this Kconfig option is N, preserving the current behavior of booting in non-secure mode by default when non-secure mode is supported. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-30/+48
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| * | imx: fix exception vectors relocation in imx27Albert ARIBAUD2014-11-20-28/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ff46cc4 fixed exception vectors setting in the general ARM case, by either copying the exception and indirect vector tables to normal (0x00000000) or high (0xFFFF0000) vectors address, or setting VBAR to U-Boot's base if applicable. i.MX27 SoC is ARM926E-JS, thus has only normal and high options, but does not provide RAM at 0xFFFF0000 and has only ROM at 0x00000000; it is therefore not possible to move or change its exception vectors. Besides, i.MX27 ROM code does provide an indirect vectors table but at a non-standard address and with the reset and reserved vectors missing. Turn the current vector relocation code into a weak routine called after relocate_code from crt0, and add strong version for i.MX27. Series-Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Tested-by: Philippe Reynes <tremyfr@gmail.com> Tested-by: Philippe Reynes <tremyfr@yahoo.fr>
| * | cosmetic: arm: fix whitespace in arch/arm/lib/relocate.SAlbert ARIBAUD2014-11-20-4/+4
| |/ | | | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-1/+1
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | dm: arm: spl: Allow simple malloc() in SPLSimon Glass2014-11-21-1/+1
| |/ | | | | | | | | | | | | | | For SPL it is sometimes useful to have a simple malloc() just to permit driver model to work, in the cases where the full malloc() is not made available by the board config. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: remove CONFIG_ARM1136 definesMasahiro Yamada2014-11-20-2/+2
| | | | | | | | | | | | | | | | | | | | CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM1136 and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | ARM: remove CONFIG_ARM926EJS definesMasahiro Yamada2014-11-20-2/+2
|/ | | | | | | | | | CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM926EJS and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: cache-cp15: Use more accurate typesThierry Reding2014-11-12-3/+3
| | | | | | | | | | | | size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Revert "lib: bootm: add missing include"Michal Simek2014-11-11-1/+0
| | | | | | | | | | | | | | | | | This is a MIME GnuPG-signed message. If you see this text, it means that your E-mail or Usenet software does not support MIME signed messages. The Internet standard for MIME PGP messages, RFC 2015, was published in 1996. To open this message correctly you will need to install E-mail or Usenet software that supports modern Internet standards. This reverts commit 1e96220a5687efae2aed45ce56e143336c40d0a7. Remove duplicated vxworks.h header. The same change was done by "ARM: prevent compiler warnings from bootm.c" (sha1: 8d196e52b58d1e50a80c2f5067b201cda521c75c) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-10-0/+138
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| * arm: debug: adjust for U-BootMasahiro Yamada2014-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Because CONFIG_MMU is never defined in U-Boot, the non-MMU code in debug.S is always used. Unfortunately, the number of arguments of the addruart macro in Linux is different between MMU and non-MMU. This causes a build error when importing some debug macros using the third argument. (For ex. arch/arm/include/debug/exynos.S) Pass the third argument to the non-MMU addruart to avoid such a problem. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * arm: debug: add Kconfig entries for lowlevel debugMasahiro Yamada2014-10-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have not had a good method to debug the early boot stage such as lowlevel_init function. I guess developers generally use dedicated debuggers for that, but it is difficult in some cases. (For example, my debugger cannot connect to the ARM processor when it is in the secure state. It sometimes happens when I need to debug the early boot stage on ARM SoCs with secure extension.) The low level debug feature in Linux would be also helpful for U-boot when we are stucking in nasty problems where the console is not available yet. You have to enable CONFIG_DEBUG_LL to use this feature. For now, only 8250-compatible UART devices are supported. You can add a header file under arch/arm/include/debug/ directory to support your UART device if necessary. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * arm: debug: replace license blocks with SPDXMasahiro Yamada2014-10-26-3/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * arm: debug: import debug files from Linux 3.16Masahiro Yamada2014-10-26-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot does not have arch/arm/kernel, include/uapi directories, This commit copies files as follows: Location in Linux -> Location in U-Boot arch/arm/kernel/debug.S -> arch/arm/lib/debug.S arch/arm/include/debug/8250.S -> arch/arm/include/debug/8250.S include/uapi/linux/serial_reg.h -> include/linux/serial_reg.h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | arm: interrupt_init: set sp in IRQ/FIQ modesGeorges Savoundararadj2014-10-29-0/+27
| | | | | | | | | | | | | | | | | | | | | | Before this commit, the stack addresses for IRQ and FIQ modes, IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init but they were not used. This commit sets the stack pointers for IRQ and FIQ modes. Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | arm: relocate the exception vectorsGeorges Savoundararadj2014-10-29-0/+30
| | | | | | | | | | | | | | | | | | | | | | This commit relocates the exception vectors. As ARM1176 and ARMv7 have the security extensions, it uses VBAR. For the other ARM processors, it copies the relocated exception vectors to the correct address: 0x00000000 or 0xFFFF0000. Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Warren <twarren@nvidia.com>
* | arm: make .vectors section allocatableGeorges Savoundararadj2014-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A regression was introduced in commit 41623c91. The consequence of that is the non-relocation of the section .vectors symbols : _undefined_instruction, _software_interrupt, _prefetch_abort, _data_abort, _not_used, _irq and _fiq. Before commit 41623c91, the exception vectors were in a .text section. The .text section has the attributes allocatable and executable [1]. In commit 41623c91, a specific section is created, called .vectors, with the attribute executable only. What have changed between commit 41623c91^ and 41623c91 is the attribute of the section which contains the exception vectors. An allocatable section is "a section [that] occupies memory during process execution" [1] which is the case of the section .vectors. Adding the lacking attribute (SHF_ALLOC or "a") for the definition of the section .vectors fixed the issue. To summarize, the fix has to mark .vectors as allocatable because the exception vectors reside in "memory during execution" and they need to be relocated. [1] http://man7.org/linux/man-pages/man5/elf.5.html Signed-off-by: Georges Savoundararadj <savoundg@gmail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-27-1/+4
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| * | ARM: prevent compiler warnings from bootm.cEric Nelson2014-10-21-1/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Without preceding declarations, "make C=1" generates "Should it be static?" warnings for symbols do_bootm_linux, boot_prep_vxworks, and boot_jump_vxworks Include of bootm.h also identified a signature mismatch (const on argv[]). Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | arm: vectors: provide protypes from vectors.SJeroen Hofstee2014-10-25-0/+1
| | | | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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