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* ARM: cache: implement a default weak flush_cache() functionWu, Josh2015-08-12-21/+5
| | | | | | | | | | | | | | | | | Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
* ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh2015-08-12-0/+9
| | | | | | | | | | | | | Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+2
| | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM: Implement non-cached memory supportThierry Reding2014-12-18-0/+44
| | | | | | | | | | | | | | | | | | | | | | Implement an API that can be used by drivers to allocate memory from a pool that is mapped uncached. This is useful if drivers would otherwise need to do extensive cache maintenance (or explicitly maintaining the cache isn't safe). The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting. Boards can set this to the size to be used for the non-cached area. The area will typically be right below the malloc() area, but architectures should take care of aligning the beginning and end of the area to honor any mapping restrictions. Architectures must also ensure that mappings established for this area do not overlap with the malloc() area (which should remain cached for improved performance). While the API is currently only implemented for ARM v7, it should be generic enough to allow other architectures to implement it as well. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: remove CONFIG_ARM1136 definesMasahiro Yamada2014-11-20-2/+2
| | | | | | | | | | CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM1136 and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: remove CONFIG_ARM926EJS definesMasahiro Yamada2014-11-20-2/+2
| | | | | | | | | | CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM926EJS and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-10/+3
| | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* arm1136: move cache code from start.S to cache.cAlbert ARIBAUD2014-05-15-3/+10
| | | | | | | arch/arm/cpu/arm1136/start.S contain a cache flushing function. Remove the function and move its code into arch/arm/lib/cache.c. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* arm: Remove OMAP2420H4 and all omap24xx supportTom Rini2013-06-10-1/+1
| | | | | | | | | The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
* arm: do not force d-cache enable on all boardsAneesh V2011-09-04-0/+12
| | | | | | | | | | | | c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() to board_init_r(). This enables d-cache for all ARM boards. As a result some of the arm boards that are not cache-ready are broken. Revert this change and allow platform code to take the decision on d-cache enabling. Also add some documentation for cache usage in ARM. Signed-off-by: Aneesh V <aneesh@ti.com>
* arm: minor fixes for cache and mmu handlingAneesh V2011-07-04-0/+11
| | | | | | | | | | | 1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: integrate cache maintenance supportAneesh V2011-07-04-5/+0
| | | | | | | | | | - Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
* arm: make default implementation of cache_flush() weakly linkedAneesh V2011-07-04-1/+3
| | | | | | | make default implementation of cache_flush() weakly linked so that sub-architectures can override it Signed-off-by: Aneesh V <aneesh@ti.com>
* ARMV7: Fix build for non-OMAP3 boardsSteve Sakoman2010-11-04-1/+1
| | | | | | | | | | | | | | | Commit c3d3a54 uses CONFIG_ARMV7 to determine whether to call the v7_flush_cache_all function. This breaks the build for all non-OMAP3 boards (like Panda and OMAP4430SDP) since there is only a v7_flush_cache_all implementation for OMAP3. This patch uses CONFIG_OMAP3XXX instead of CONFIG_ARMV7 so that only boards with a v7_flush_cache_all will make the call. Tested on Beagle, Overo, Panda, and OMAP4430SDP Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* armv7, beagle: add support for ELF relocationsHeiko Schocher2010-10-13-1/+1
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM (ARM11): add data cache support, test on Qong boardHeiko Schocher2010-09-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Add data cache support for arm1136 systems. Enable "cache" command on Qong board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 177s 95s 43s = x 4.1 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- QONG (ARM11) 1.54s 0.95s 0.18s = x 8.6 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de>
* ARM V7 (OMAP): add data cache support, test on Beagle boardHeiko Schocher2010-09-19-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add data cache support for ARM V7 systems. Used cache flush functions from linux:arch/arm/mm/cache-v7.S developed from Catalin Marinas. Enable "cache" command on Beagle board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 116s 106s 30.3s = x 3.8 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- Beagle (Cortex A8) 1.84s 1.64s 0.12s = x 15.3 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Ben Gardiner<bengardiner@nanometrics.ca>
* ARM (ARM926ejs): add data cache support, tested on magnesium and tx25 boardHeiko Schocher2010-09-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable "cache" command on tx25 and magnesium board and test performance. Test 1: Loading 127 MB of data from NAND flash into RAM: Instr. Cache off on on Data Cache off off on -------------------------------------------------- magnesium 32,6s 22,5s 30s = x 1,09 tx25 (29MB only) 9,69s 5,05s 8,16s = x 1,19 Test 2: uncompressing a gzipped image from RAM to RAM (size compressed: 6.5 MiB, uncompressed: 35 MiB): Instr. Cache off on on Data Cache off off on -------------------------------------------------- magnesium 4,25s 2,08s 1,72s = x 2,47 tx25 4,82s 2,04s 1,84s = x 2,62 Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Alessandro Rubini <rubini@gnudd.com>
* Move lib_$ARCH directories to arch/$ARCH/libPeter Tyser2010-04-13-0/+36
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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