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path: root/arch/arm/lib/cache-cp15.c
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* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-0/+5
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: cache: always flush cache line size for page tableStefan Agner2016-08-26-1/+13
| | | | | | | | | | | | The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* arm: cache: add support for LPAE for region D$ behaviorStefan Agner2016-08-26-0/+4
| | | | | | | Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* arm: Add support for HYP mode and LPAE page tablesAlexander Graf2016-03-27-6/+60
| | | | | | | | | | | | | | We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7Marek Vasut2016-01-31-1/+1
| | | | | | | | | | | | | | | | | | | | | The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko2015-04-16-0/+14
| | | | | | | | The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
* ARM: cache-cp15: Use more accurate typesThierry Reding2014-11-12-3/+3
| | | | | | | | | | | | size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
* arm: cache: Add support for write-allocate D-CacheMarek Vasut2014-10-06-0/+2
| | | | | | | | | | | | | | Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* ARM: Fix overflow in MMU setupMarek Vasut2014-08-30-1/+1
| | | | | | | | | | | | | | | | | | The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables. The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted. Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-7/+2
| | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: mmu: Set domain permissions to client accessR Sricharan2013-03-28-0/+7
| | | | | | | | | | | | | | | | | The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* ARM: mmu: Introduce weak dram_bank_setup functionR Sricharan2013-03-28-1/+3
| | | | | | | | | | | | | | Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* arm: Move tlb_addr and tlb_size to arch_global_dataSimon Glass2013-02-01-3/+3
| | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Address tlb_size in this patch as well] Signed-off-by: Tom Rini <trini@ti.com>
* arm: move flush_dcache_all() to just before disable cacheArun Mankuzhi2013-01-10-1/+4
| | | | | | | | | | | | | | | | | | | In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Add control over cachability of memory regionsSimon Glass2012-11-19-11/+40
| | | | | | | | | | | | | | Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: cache: Move the cp15 CR register read before flushing the cache.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c int cleanup_before_linux(void) { ... ... dcache_disable(); v7_outer_cache_disable(); invalidate_dcache_all(); } 1) invalidate_dcache_all call expects that all the caches has been flushed, invalidated and there are no dirty entries prior to its execution. In the above sequence dcache_disable() flushes, invalidates the caches and turns off the mmu. But after it cleanups the cache and before the mmu is disabled there is a cp_delay() function which has STR instruction. On certain cores like the cortex-a15, cache hit and a write can happen to a cache line even when the dcache is disabled. So the above mentioned STR instruction creates a dirty entry after cleaning. The mmu gets disabled after this. 2) invalidate_dcache_all invalidates the cache lines. Again on cores like cortex-a15, invalidate instruction flushes the dirty line as well. So some times the dirty line from sequence 1 can corrupt the memory resulting in a crash. Fixing this by moving the get_cr() and cp_delay() calls before cleaning up the cache, thus avoiding the dirty entry. Signed-off-by: R Sricharan <r.sricharan@ti.com>
* arm: minor fixes for cache and mmu handlingAneesh V2011-07-04-2/+7
| | | | | | | | | | | 1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: integrate cache maintenance supportAneesh V2011-07-04-0/+7
| | | | | | | | | | - Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
* armv7: rename cache related CONFIG flagsAneesh V2011-07-04-3/+3
| | | | | | | | | | | | | | | | Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
* Drop support for CONFIG_SYS_ARM_WITHOUT_RELOCWolfgang Denk2010-10-29-19/+0
| | | | | | | | | | | | | | | | When this define was introduced, the idea was to provide a soft migration path for ARM boards to get adapted to the new relocation support. However, other recent changes led to a different implementation (ELF relocation), where this no longer works. By now CONFIG_SYS_ARM_WITHOUT_RELOC does not only not help any more, but it actually hurts because it obfuscates the actual code by sprinkling it with lots of dead and non-working debris. So let's make a clean cut and drop CONFIG_SYS_ARM_WITHOUT_RELOC. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
* ARM: add relocation supportHeiko Schocher2010-09-19-3/+34
| | | | | | | | | | | | | | | | | | | !! This breaks support for all arm boards !! To compile in old style, you must define CONFIG_SYS_ARM_WITHOUT_RELOC or you can compile with "CONFIG_SYS_ARM_WITHOUT_RELOC=1 ./MAKEALL board" !! This define will be removed soon, so convert your board to use relocation support Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de> Fix boot from NAND for non-ARM systems Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: cp15: setup mmu and enable dcacheHeiko Schocher2010-09-19-0/+51
| | | | | | | | | | | | | | | | | | | | | This has been tested on at91sam9263 and STN8815. Again, I didn't check if it has bad effects on non-arm926 cores. Initially I had a "done" bit to only set up page tables at the beginning. However, since the aligmnent requirement was for the whole object file, this extra integer tool 16kB in BSS, so I chose to remove it. Also, note not all boards use PHYS_SDRAM, but it looks like it's the most used name (more than CONFIG_SYS_DRAM_BASE for example). Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Heiko Schocher <hs@denx.de>
* Move lib_$ARCH directories to arch/$ARCH/libPeter Tyser2010-04-13-0/+120
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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