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* sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-26-0/+5
| | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-26-1/+3
| | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-26-0/+8
| | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-26-1/+12
| | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* imx: mx7: default enable MDIO open drainPeng Fan2016-01-24-0/+2
| | | | | | | | | | The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul/sx: fix mmdc_ch0 clk calculationPeng Fan2016-01-24-0/+12
| | | | | | | | | | | | | Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: add more entry for mxc_ccm_regPeng Fan2016-01-24-0/+91
| | | | | | | | Add more entries for structure mxc_ccm_reg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-24-2/+2
| | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: apbh_dma: Update APBH-DMA for MX7DPeng Fan2016-01-24-4/+4
| | | | | | | Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+17
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Tidy up the register-access macrosSimon Glass2016-01-21-3/+4
| | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a video-output driverSimon Glass2016-01-21-0/+349
| | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-0/+636
| | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+456
| | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-21-29/+29
| | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-21-0/+41
| | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clock: Add a function to find a clock by IDSimon Glass2016-01-21-0/+12
| | | | | | | | The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-21-4/+8
| | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
* sunxi: Add support for the I2C controller which is part of the PRCMJelle van der Waa2016-01-21-0/+8
| | | | | | | | | | | Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: Minor cleanups] Signed-off-by: Hans de Goede <hdegoede@redhat.com> applied with fixing 2 checkpatch warnings: WARNING: please, no space before tabs Signed-off-by: Heiko Schocher <hs@denx.de>
* arm, ubifs: fix gcc5.x compiler warningHeiko Schocher2016-01-20-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | compiling U-Boot for openrd_base_defconfig with gcc 5.x shows the following warning: CC fs/ubifs/super.o In file included from fs/ubifs/ubifs.h:35:0, from fs/ubifs/super.c:37: fs/ubifs/super.c: In function 'atomic_inc': ./arch/arm/include/asm/atomic.h:55:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized] local_irq_save(flags); ^ fs/ubifs/super.c: In function 'atomic_dec': ./arch/arm/include/asm/atomic.h:64:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized] local_irq_save(flags); ^ CC fs/ubifs/sb.o [...] CC fs/ubifs/lpt.o In file included from include/linux/bitops.h:123:0, from include/common.h:20, from include/ubi_uboot.h:17, from fs/ubifs/ubifs.h:37, from fs/ubifs/lpt.c:35: fs/ubifs/lpt.c: In function 'test_and_set_bit': ./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized] local_irq_save(flags); ^ CC fs/ubifs/lpt_commit.o In file included from include/linux/bitops.h:123:0, from include/common.h:20, from include/ubi_uboot.h:17, from fs/ubifs/ubifs.h:37, from fs/ubifs/lpt_commit.c:26: fs/ubifs/lpt_commit.c: In function 'test_and_set_bit': ./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized] local_irq_save(flags); ^ CC fs/ubifs/scan.o CC fs/ubifs/lprops.o CC fs/ubifs/tnc.o In file included from include/linux/bitops.h:123:0, from include/common.h:20, from include/ubi_uboot.h:17, from fs/ubifs/ubifs.h:37, from fs/ubifs/tnc.c:30: fs/ubifs/tnc.c: In function 'test_and_set_bit': ./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used uninitialized in this function [-Wuninitialized] local_irq_save(flags); ^ CC fs/ubifs/tnc_misc.o Fix it. Signed-off-by: Heiko Schocher <hs@denx.de>
* armv8: Add Secure Monitor/Hypervisor Call (SMC/HVC) infrastructureSergey Temerkhanov2016-01-19-0/+21
| | | | | | | | | | | | | | | | | This commit adds functions issuing calls to secure monitor or hypervisore. This allows using services such as Power State Coordination Interface (PSCI) provided by firmware, e.g. ARM Trusted Firmware (ATF) The SMC call can destroy all registers declared temporary by the calling conventions. The clobber list is "x0..x17" because of this Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* armv8: New MMU setup code allowing to use 48+ bits PA/VASergey Temerkhanov2016-01-19-6/+86
| | | | | | | | | | | | | This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc. Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
* armv8: Add read_mpidr() functionSergey Temerkhanov2016-01-19-0/+11
| | | | | | | | | | This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com> Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-273/+24
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: lpc32xx: switch SPL builds to driver modelVladimir Zapolskiy2016-01-13-18/+1
| | | | | | | | | | | | | | | | For NXP LPC32xx boards the change enables SPL_DM option, this allows to use any driver model UART driver in SPL images, hence a restriction on HSUART in SPL image is removed and well as definitions for non-DM NS16550 driver, its DM version is used instead. Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE for LPC32xx boards. The change adds about 5KB to the resulting SPL image (for devkit3250 board SPL image is increased from 10672 to 15608 bytes). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: lpc32xx: switch serial console to driver modelVladimir Zapolskiy2016-01-13-15/+18
| | | | | | | | | | | | | | | | | On NXP LPC32xx platform for non-SPL builds the change adds standard (NS16550) and high-speed UARTs to driver model. Due to specific of DM NS16550 device description UART clock can not be got in runtime and by default it is set to 13MHz, if board PERIPH_CLK is different, this should be specified in board configuration file. For SPL builds HSUARTs are disabled and non-DM NS16550 driver is compiled, if needed. The change also updates default configs of devkit3250 and work_92105 boards to reflect updates in platform files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-03-4/+6
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| * ARM: mxs: allow boards to select DC-DC switching clock sourceMichael Heimpold2016-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, override the mxs_power_setup_dcdc_clocksource function in your board support files. Example: void mxs_power_setup_dcdc_clocksource(void) { mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ); } Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * imx: mx6: fix reg base address when runtime usagePeng Fan2015-12-07-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Should use parenthese to wrap the macro definition, otherwise we will encounter error like the following: " if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; } " Without this patch, we will always encounter "Wrong LCD interface". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | armv8/ls1043a: Implement workaround for PEX erratum A009929Mingkai Hu2015-12-17-0/+2
| | | | | | | | | | | | | | | | | | Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/fsl_lsch2: fix DCSR_DCFG addressMingkai Hu2015-12-17-1/+1
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-14-12/+84
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| * | armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian2015-12-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-13-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-13-0/+12
| | | | | | | | | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-13-0/+5
| | | | | | | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | stm32: Convert serial driver to DMKamil Lulko2015-12-12-1/+9
|/ / | | | | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Add support for Allwinner A83T DRAMvishnupatekar2015-12-10-0/+203
| | | | | | | | | | | | | | | | | | | | | | Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: clk: add basic clocks for A83Tvishnupatekar2015-12-10-1/+307
| | | | | | | | | | | | | | | | | | | | | | Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar2015-12-10-0/+1
| | | | | | | | | | | | | | | | | | | | On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCsHans de Goede2015-12-10-4/+0
| | | | | | | | | | | | | | | | | | | | | | According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Chen-Yu Tsai <wens@csie.org>
* | zynq: sdhci: Move driver to DMMichal Simek2015-12-07-4/+0
| | | | | | | | | | | | | | Move driver to DM Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: zynq: Remove unused SERIAL macros for serial_zynqMichal Simek2015-12-07-3/+0
| | | | | | | | | | | | Remove unused macros when driver was moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Change e-mail address of Kamil LulkoKamil Lulko2015-12-05-5/+5
| | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-04-1/+1
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| * iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-25-1/+1
| | | | | | | | | | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
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