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* Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-05-15-0/+147
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| * Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-0/+147
| |\ | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| | * usb: ehci: rmobile: Add support ehci host driver of rmobile SoCsNobuhiro Iwamatsu2014-04-30-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | | imx25: Add new hardware registersThomas Diener2014-05-09-0/+175
| | | | | | | | | | | | Signed-off-by: Thomas Diener <dietho@gmx.de>
* | | iomux-v3: Add support for mx6sl LVE bitFabio Estevam2014-05-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-04-29-2814/+2672
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| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-74/+1217
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| | * | arm, da850: staticize funtionsManish Badarkhe2014-04-17-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make funtions static which are locally used in file and remove the declaration from header file. Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com>
| | * | keystone2: net: add keystone ethernet driverKaricheri, Muralidharan2014-04-17-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
| | * | keystone2: add keystone multicore navigator driverVitaly Andrianov2014-04-17-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multicore navigator consists of Network Coprocessor (NetCP) and Queue Manager sub system. More details on the hardware can be obtained from the following links:- Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6 Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9 Multicore navigator driver implements APIs to configure the Queue Manager and NetCP Pkt DMA. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| | * | k2hk: add support for k2hk SOC and EVMVitaly Andrianov2014-04-17-0/+777
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
| | * | i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan2014-04-17-68/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| | * | OMAP3: beagle-xm: generate fake USB ethernet MAC address from dieidNishanth Menon2014-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to OMAP5uEVM, PandaBoard, BeagleBoard-XM has a USB based ethernet without MAC address embedded. So fake a MAC address following the similar strategy used on OMAP5 and PandaBoard family. Signed-off-by: Nishanth Menon <nm@ti.com>
| | * | omap3/sys_info: provide interface to read die idNishanth Menon2014-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | introduce get_die_id() function which allows generation of information such as fake MAC address from the processor ID code. Signed-off-by: Nishanth Menon <nm@ti.com>
| | * | OMAP: common: consolidate fake USB ethernet MAC address creationNishanth Menon2014-04-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI platforms such as OMAP5uevm, PandaBoard, use equivalent logic to generate fake USB MAC address from device unique DIE ID. Consolidate this to a generic location such that other TI platforms such as BeagleBoard-XM can also use the same. NOTE: at this point in time, I dont yet see a need for a generic dummy ethernet MAC address creation function, but if there is a need in the future, this can be further abstracted out. Signed-off-by: Nishanth Menon <nm@ti.com>
| | * | ARM: OMAP: hide custom bit manipulation function sr32()Wolfgang Denk2014-04-17-3/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | The only remaining user of the custom bit manipulation function sr32() is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in that file to prepare complete removal. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * | ARM: tegra: pack pinmux data tables tighterStephen Warren2014-04-17-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | usb: tegra: combine header fileStefan Agner2014-04-17-753/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | usb: tegra: fix PHY configurationStefan Agner2014-04-17-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-04-17-330/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-04-17-321/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Tegra30 pinmux cleanupStephen Warren2014-04-17-391/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra30_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted one entry in pinmux-config-cardhu.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-135/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pinmux naming consistency fixesStephen Warren2014-04-17-56/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: reduce public pinmux APIStephen Warren2014-04-17-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove a few unused functions from the pinmux header. They aren't currently used, and removing them prevents any new usage from appearing. This will ease moving to just pinmux_config_table() and padgrp_config_table() in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pinctrl: remove duplicationStephen Warren2014-04-17-698/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: use apb_misc.h in more placesStephen Warren2014-04-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch. This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: prototype pinmux_init() in board.hStephen Warren2014-04-17-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | pinmux_init() is a board-level function, not a pinmux driver function. Move the prototype to a board header rather than the driver header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20Stephen Warren2014-04-17-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For consistency with other SoCs, modify Tegra20's enum pmux_func to: * Remove PMUX_FUNC values that aren't real * Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0; this will be assumed by pinmux_set_func() in a future patch. Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a private define inside the driver to prevent this from causing compilaton errors. This will be cleaned up when the pin tables are re-written in a later patch in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pinctrl: remove vddioStephen Warren2014-04-17-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: pinctrl: remove func_safeStephen Warren2014-04-17-4/+0
| |/ | | | | | | | | | | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | mx6slevk: Add SPI NOR flash supportFabio Estevam2014-04-28-0/+4
| | | | | | | | | | | | | | | | | | | | mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | imx-common/video: add detect_hdmiEric Benard2014-04-15-0/+4
| | | | | | | | | | | | | | | | this function is used by several board together with board_video_skip to detect if hdmi is plugged is order to select the display to use. So move it in imx-common to share it. Signed-off-by: Eric Bénard <eric@eukrea.com>
* | imx-common: add board_video_skipEric Benard2014-04-15-0/+20
|/ | | | | | | | this function is shared by several boards and thus can be factorized Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-08-10/+15
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
| * cpu: exynos4: add ace sha base addressPrzemyslaw Marczak2014-03-28-4/+4
| | | | | | | | | | Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * spl: Fix guardian macros in spl.hMarek Vasut2014-03-28-6/+6
| | | | | | | | | | | | | | | | | | Fix the macros guarding the spl.h header for various platforms. Due to a typo and a propagation of it, the macros went out-of-sync with their ifdef check, so fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
| * mmc: Split mmc struct, rework mmc initialization (v2)Pantelis Antoniou2014-03-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that struct mmc was implemented was a bit of a mess; configuration and internal state all jumbled up in a single structure. On top of that the way initialization is done with mmc_register leads to a lot of duplicated code in drivers. Typically the initialization got something like this in every driver. struct mmc *mmc = malloc(sizeof(struct mmc)); memset(mmc, 0, sizeof(struct mmc); /* fill in fields of mmc struct */ /* store private data pointer */ mmc_register(mmc); By using the new mmc_create call one just passes an mmc config struct and an optional private data pointer like this: struct mmc = mmc_create(&cfg, priv); All in tree drivers have been updated to the new form, and expect mmc_register to go away before long. Changes since v1: * Use calloc instead of manually calling memset. * Mark mmc_register as deprecated. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | arm64 patch: gicv3 supportDavid Feng2014-04-08-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add gicv3 support to uboot armv8 platform. Changes for v2: - rename arm/cpu/armv8/gic.S with arm/lib/gic_64.S - move smp_kick_all_cpus() from gic.S to start.S, it would be implementation dependent. - Each core initialize it's own ReDistributor instead of master initializeing all ReDistributors. This is advised by arnab.basu <arnab.basu@freescale.com>. Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | arm: vf610: add enet1 supportMarcel Ziswiler2014-04-07-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains several changes required for second Ethernet (enet1/RMII1) port on vf610 - ANADIG PLL5 control definitions required for Ethernet RMII1 clock - Secondary Ethernet (enet1) MAC RMII1 base address definition - RMII1 iomux definitions - VF610_PAD_PTA6__RMII0_CLKOUT iomux definition required for internal (e.g. crystal-less) Ethernet clocking. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | arm: vf610: add uart0 clock/iomux definitionsMarcel Ziswiler2014-04-07-0/+3
| | | | | | | | | | | | | | | | | | Add CCM_CCGR0_UART0_CTRL_MASK clock definition and add TX/RX iomux definitions for UART0 (aka. SCI0). Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | arm: vf610: fix anadig register structMarcel Ziswiler2014-04-07-25/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The anadig_reg structure started at the wrong offset (fixed by adding reserved_0x000[4]), was missing some reserved field required for alignment purpose (reserved_0x094[3] between pll4_denom and pll6_ctrl) and further contained a too short reserved field causing further miss- alignment (reserved_0x0C4[7]). Also, rename all the reserved fields and using a memory offset based scheme for. Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> [stefan@agner.ch: regrouped patch] Signed-off-by: Stefan Agner <stefan@agner.ch>
* | armv8/cache: Change cache invalidate and flush functionYork Sun2014-04-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | When SoC first boots up, we should invalidate the cache but not flush it. We can use the same function for invalid and flush mostly, with a wrapper. Invalidating large cache can ben slow on emulator, so we postpone doing so until I-cache is enabled, and before enabling D-cache. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | socfpga: Adding Clock Manager driverChin Liang See2014-04-07-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Manager driver will be called to reconfigure all the clocks setting based on user input. The input are passed to Preloader through handoff files Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-25-1/+1
|\ \ | |/ | | | | | | | | | | | | Trivial merge conflict, needed to manually remove local_info as per commit 41364f0f. Conflicts: board/samsung/common/board.c
| * kirkwood: kwbimage: refactor CONFIG_SYS_KWD_CONFIGMasahiro Yamada2014-03-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull out "$(SRCTREE)/" from CONFIG_SYS_KWD_CONFIG and push it into the top Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michael Walle <michael@walle.cc> Cc: Simon Guinot <simon.guinot@sequanux.org> Cc: Dave Purdy <david.c.purdy@gmail.com> Cc: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net> Cc: Luka Perkov <luka@openwrt.org> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Jason Cooper <u-boot@lakedaemon.net> Cc: Siddarth Gore <gores@marvell.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Eric Cooper <ecc@cmu.edu> Cc: Suriyan Ramasami <suriyan.r@gmail.com>
* | arm:exynos: add common DTS file for exynos 4Piotr Wilczek2014-03-12-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds common dtsi file and config header for all Exynos 4 based boards. Patch additionaly adds board specific (weak) functions for board_early_init_f and board_power_init functions. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | drivers:mmc:sdhci: enable support for DTPiotr Wilczek2014-03-12-0/+7
| | | | | | | | | | | | | | | | | | This patch enables support for device tree for sdhci driver. Non DT case is still supported. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | video:mipidsim:fdt: Add DT support for mipi dsim driverPiotr Wilczek2014-03-12-0/+5
|/ | | | | | | | | This patch enables parsing mipi data from device tree. Non device tree case is still supported. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-10-1/+29
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