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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-26-64/+137
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| * ARMv7: PSCI: ls102xa: move secure text section into OCRAMHongbo Zhang2016-07-26-1/+1
| | | | | | | | | | | | | | | | | | LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implementionHongbo Zhang2016-07-26-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: ls102xa: check target CPU ID before further operationsHongbo Zhang2016-07-26-0/+5
| | | | | | | | | | | | | | | | | | The input parameter CPU ID needs to be validated before furher oprations such as CPU_ON, this patch introduces the function to do this. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: PSCI: add PSCI v1.0 functions skeletonHongbo Zhang2016-07-26-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not implemented" by default, as a common framework all the dummy functions are added here, it is up to every platform developer to decide which version of PSCI and which functions to implement. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl_lsch2: Add LS1046A SoC supportMingkai Hu2016-07-26-1/+32
| | | | | | | | | | | | | | | | | | | | | | The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl_lsch2: Add SerDes 2 supportQianyu Gong2016-07-26-0/+3
| | | | | | | | | | | | | | | | | | New SoC LS1046A belongs to Freescale Chassis Generation 2 and has two SerDes so we need to add this support in fsl_lsch2. The SoC related SerDes 2 support will be added in SoC patch. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Consolidate the LSCH2 common definesQianyu Gong2016-07-26-39/+20
| | | | | | | | | | | | | | | | | | Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common configurations. So put the common define under FSL_LSCH2 to increase readability. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Add A72 core detectionAlison Wang2016-07-26-0/+2
| | | | | | | | | | | | | | | | | | | | Add support to detect Cortex-A72 core for printing it out. The Initiator Version of A72 core should be 0x4. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-14/+29
| | | | | | | | | | | | | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-2/+23
| | | | | | | | | | | | | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
| * include: usb: Rename USB controller base address mappingRajesh Bhagat2016-07-26-9/+7
| | | | | | | | | | | | | | | | Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2016-07-26-6/+6
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| * | omap5/dra7: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap5[1]/dra7[2] TRM, correct the offsets as per the documentation. [1] - http://www.ti.com/lit/pdf/swpu249 [2] - http://www.ti.com/lit/pdf/spruhz6 Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | omap4: i2c: correct register offset for sync registerMugunthan V N2016-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register offset of i2c_sysc offset is not correct as per omap4 TRM [1], correct the offsets as per the documentation. [1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | rockchip: Add a way to obtain the main clock deviceSimon Glass2016-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner2016-07-25-1/+1
|/ / | | | | | | | | | | | | | | | | | | The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* | sunxi: Add missing macros to configure the NAND controller clkBoris Brezillon2016-07-24-0/+5
|/ | | | | | | We need some macros to manipulate the NAND controller clock. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* armv7: armv7: introduce set_gpmc_cs0Ladislav Michl2016-07-22-0/+1
| | | | | | Allow boards to runtime detect flash type. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-4/+3
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv7: add reset timeout to identify_nand_chipLadislav Michl2016-07-22-1/+1
| | | | | | | | | | identify_nand_chip hangs forever in loop when NAND is not present. As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout to let function fail gracefully allowing caller to know NAND is not present. On NAND equipped board, reset succeeds on first read, so 1000 loops seems to be safe timeout. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-1/+0
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| * ARM64: zynqmp: Remove get_uart_clk()Michal Simek2016-07-22-1/+0
| | | | | | | | | | | | ZynqMP will use reading clock freq directly from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-07-21-0/+179
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| * ARM: tegra: add IVC protocol implementationStephen Warren2016-07-21-0/+179
| | | | | | | | | | | | | | | | | | | | | | | | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter Processor Communication) framework. Within the context of U-Boot, it is typically used for communication between the main CPU and various auxiliary processors. In particular, it will be used to communicate with the BPMP (Boot and Power Management Processor) on Tegra186 in order to manipulate clocks and reset signals. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"Tom Rini2016-07-21-2/+0
|/ | | | | | | | | | Per Vikas' request, the problem this commit is supposed to be solving is something he doesn't see and further this introduces additional hardware requirements. This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-124/+245
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * ARMv8/PSCI: Fixup the device tree for PSCIHou Zhiqiang2016-07-19-0/+1
| | | | | | | | | | | | | | | | Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8/layerscape: Add FSL PPA supportHou Zhiqiang2016-07-19-0/+20
| | | | | | | | | | | | | | | | | | | | | | The FSL Primary Protected Application (PPA) is a software component loaded during boot which runs in TrustZone and remains resident after boot. Use the secure firmware framework to integrate FSL PPA into U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv8: add the secure monitor firmware frameworkHou Zhiqiang2016-07-19-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This framework is introduced for ARMv8 secure monitor mode firmware. The main functions of the framework are, on EL3, verify the firmware, load it to the secure memory and jump into it, and while it returned to U-Boot, do some necessary setups at the 'target exception level' that is determined by the respective secure firmware. So far, the framework support only FIT format image, and need to define the name of which config node should be used in 'configurations' and the name of property for the raw secure firmware image in that config. The FIT image should be stored in Byte accessing memory, such as NOR Flash, or else it should be copied to main memory to use this framework. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: layerscape: Convert to use common MMU frameworkYork Sun2016-07-19-123/+187
| | | | | | | | | | | | | | | | Drop platform code to create static MMU tables. Use common framework to create MMU tables on the run. Tested on LS2080ARDB with secure and non-secure ram scenarios. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: mmu: Add support of non-identical mappingYork Sun2016-07-15-1/+2
| | | | | | | | | | | | | | Introduce virtual and physical addresses in the mapping table. This change have no impact on existing boards because they all use idential mapping. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: mmu: house cleaningYork Sun2016-07-15-0/+2
| | | | | | | | | | | | | | | | Make setup_pgtages() and get_tcr() available for platform code to customize MMU tables. Remove unintentional call of create_table(). Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: Add tlb_allocated to arch global dataYork Sun2016-07-15-0/+1
| | | | | | | | | | | | | | | | | | When secure ram is used, MMU tables have to be put into secure ram. To use common MMU code, gd->arch.tlb_addr will be used to host TLB entry pointer. To save allocated memory for later use, tlb_allocated variable is added to global data structure. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: Move secure_ram variable out of generic global dataYork Sun2016-07-15-0/+14
| | | | | | | | | | | | | | Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: York Sun <york.sun@nxp.com>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-5/+29
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| * | ARM: PSCI: Make psci_get_cpu_stack_top local to armv7/psci.SChen-Yu Tsai2016-07-15-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a secure data section for storing variables, there should be no need for platform code to get the stack address. Make psci_get_cpu_stack_top a local function, as it should only be used in armv7/psci.S and only by psci_stack_setup. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | ARM: PSCI: Add helper functions to access per-CPU target PC storageChen-Yu Tsai2016-07-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have a data section, add helper functions to save and fetch per-CPU target PC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | ARM: Add secure section for initialized dataChen-Yu Tsai2016-07-15-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The secure monitor may need to store global or static values within the secure section of memory, such as target PC or CPU power status. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | ARM: Move __secure definition to common asm/secure.hChen-Yu Tsai2016-07-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | sunxi and i.mx7 both define the __secure modifier to put functions in the secure section. Move this to a common place. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | ARM: Add an empty secure stack sectionChen-Yu Tsai2016-07-15-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now we've been using memory beyond psci_text_end as stack space for the secure monitor or PSCI implementation, even if space was not allocated for it. This was partially fixed in ("ARM: allocate extra space for PSCI stack in secure section during link phase"). However, calculating stack space from psci_text_end in one place, while allocating the space in another is error prone. This patch adds a separate empty secure stack section, with space for CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also __secure_stack_start and __secure_stack_end symbols. The linker script handles calculating the correct VMAs for the stack section. For platforms that relocate/copy the secure monitor before using it, the space is not allocated in the executable, saving space. For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page of stack space for 4 CPUs is allocated, matching the previous behavior. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Use BROM stored boot_media value to determine our boot-sourceHans de Goede2016-07-15-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we know that the BROM stores a value indicating the boot-source at the beginning of SRAM, use that instead of trying to recreate the BROM's boot probing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | net: Add EMAC driver for H3/A83T/A64 SoCs.Amit Singh Tomar2016-07-15-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: FEL - Add the ability to recognize and auto-import uEnv-style dataBernhard Nortmann2016-07-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch converts one of the "reserved" fields in the sunxi SPL header to a fel_uEnv_length entry. When booting over USB ("FEL mode"), this enables the sunxi-fel utility to pass the string length of uEnv.txt compatible data; at the same time requesting that this data be imported into the U-Boot environment. If parse_spl_header() in the sunxi board.c encounters a non-zero value in this header field, it will therefore call himport_r() to merge the string (lines) passed via FEL into the default settings. Environment vars can be changed this way even before U-Boot will attempt to autoboot - specifically, this also allows overriding "bootcmd". With fel_script_addr set and a zero fel_uEnv_length, U-Boot is safe to assume that data in .scr format (a mkimage-type script) was passed at fel_script_addr, and will handle it using the existing mechanism ("bootcmd_fel"). Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-8/+6
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| * | rockchip: sdram: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Note that only SPL needs to fiddle with the SDRAM registers, so decoding the platform data fully is not necessary in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Update the sdram-channel property to support of-platdataSimon Glass2016-07-14-0/+6
| |/ | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Add a comment to the code to explain the purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move check_cache_range() into a common placeSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | This code is common, so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
generated by cgit v1.1 at 2024-11-04 20:05:30 +0000