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| * | | imx: Move some header files from arch-mxs to imx-commonStefan Roese2013-04-22-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following headers are moved to a i.MX common location: - regs-common.h - regs-apbh.h - regs-bch.h - regs-gpmi.h - dma.h This way this header can be re-used also by other i.MX platforms. For example the i.MX6 which will need it for the upcoming NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6: Add solo-lite variant supportFabio Estevam2013-04-22-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6 solo-lite is another member of the mx6 series. For more information about mx6 solo-lite, please visit: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SL&nodeId=018rH3ZrDRB24A Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | iomux-v3: Place pad control definitions into common fileFabio Estevam2013-04-22-55/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of having the same PAD control definition in each MX6 variant pin file, place it into a common location. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | Merge branch 'next'Stefano Babic2013-04-21-2/+2
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| | * | arm: imx: Change iomux functions to void typeStefan Roese2013-04-16-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They never return anything also than 0, so lets change the function to void instead. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-11/+0
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| * | | | pxa27x_udc: remove call to unimplemented set_GPIO_mode()Mike Dunn2013-05-05-11/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_USB_DEV_PULLUP_GPIO is defined, a link error occurs because the set_GPIO_mode() helper function is not implemented. This function doesn't do much except make the code a little more readable, so I just manually coded its equivalent and removed the prototype from the header file. It is invoked no where else in the code. While I was at it, I noticed that two other function prototypes in the same header file are also neither implemented nor invoked anywhere, so I removed them as well. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
* | | | fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-2/+11
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | i2c: zynq: Add support for Xilinx ZynqMichal Simek2013-04-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* | | mmc: Add support for Xilinx Zynq sdhci controllerMichal Simek2013-04-30-0/+5
| | | | | | | | | | | | | | | | | | | | | Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | zynq: Move macros to hardware.hMichal Simek2013-04-30-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add all fixed addresses to hardware.h and change petalinux configuration to support this. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | zynq: Move scutimer baseaddr to hardware.hMichal Simek2013-04-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move baseaddr to hardware.h to be shared between configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addressesMichal Simek2013-04-30-6/+6
|/ / | | | | | | | | | | | | | | XPSS prefix was used in past and it is obsolete for quite some time. Let's use correct SoC name which is Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-2/+18
| | | | | | | | | | | | | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra114: Initialize System Counter (TSC) with osc frequencyTom Warren2013-04-15-0/+39
| | | | | | | | | | | | | | | | | | T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | Tegra: Configure L2 cache control reg properly.Tom Warren2013-04-15-0/+1
| | | | | | | | | | | | | | | | | | | | Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: support T33 SKU of Tegra30Stephen Warren2013-04-15-0/+1
|/ | | | | | | | | | | | | | | | | | | Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-0/+2
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| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | am335x: Really correct DDR timings on new BeagleBone partTom Rini2013-04-12-7/+7
| | | | | | | | | | | | | | | | The previous timings were done on the internal-only A1 board which has different DDR part than all later revs. The timings need a slight adjustment to be correct in all cases with later revs. Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-10/+15
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| * | am335x: Update timings for the beaglebone againTom Rini2013-04-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | After further testing we can run DDR at 400MHz so update the timings again. Tested-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com>
| * | am335x/ti814x: Correct MMC_BOOT_DEVICES_START/ENDTom Rini2013-04-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Given that on TI814x we have MMC1/2 swapped, we also need to swap them in MMC_BOOT_DEVICES_START/END Reported-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
* | | arm: Remove support for unused s3c64xxBenoît Thébaudeau2013-04-12-1048/+0
| | | | | | | | | | | | | | | | | | | | | | | | Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so remove associated code. It will still be possible to restore it later from the Git history if necessary. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | | arm: Remove support for smdk6400Benoît Thébaudeau2013-04-12-13/+0
|/ / | | | | | | | | | | | | | | The migration of boards from Makefile to boards.cfg was due for v2012.03, but smdk6400 did not follow, and it does not build, so move it to scrapyard. It will still be possible to restore it from the Git history before fixing it. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMCTom Rini2013-04-08-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the case of booting from certain peripherals, such as UART, we must not see what the device descriptor says for RAW or FAT mode because in addition to being nonsensical, it leads to a hang. This is why we have a test currently for the boot mode being within range. The problem however is that on some platforms we get MMC2_2 as the boot mode and not the defined value for MMC2, and in others we get the value for MMC2_2. This is required to fix eMMC booting on omap5_uevm. Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC). Signed-off-by: Tom Rini <trini@ti.com>
* | arm: omap4: Fix SDRAM AUTO DETECTIONLokesh Vutla2013-04-08-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards@prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | omap2420-h4: Fix booting from NOR flashHunter, Jon2013-04-08-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap2420-h4 board is using a RAM based address as the linker location for code. This is causing several problems when attempting to run the latest u-boot code base on this board from flash. Update the default linker location for code to be in NOR flash. Please note that OMAP maps the NOR flash to address 0x08000000 by default and so use this as the default address for the NOR flash. Also remove legacy code that attempts to calculate where in flash the sdata structure, that holds the memory interface configuration data, is located. By changing the default linker location for code to flash this is no longer necessary. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* | omap_gpmc: change nandecc commandAndreas Bießmann2013-04-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
* | omap3/omap_gpmc.h: add ooblayout for BCH8 as in kernelAndreas Bießmann2013-04-08-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds BCH8 ooblayout for NAND as provided by 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c in linux kernel. This Layout is currently only provided for 64 byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Reviewed-by: Tom Rini <trini@ti.com>
* | asm/omap_gpmc.h: consolidate common definesAndreas Bießmann2013-04-08-114/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | omap3/cpu.h: add BCH supportAndreas Bießmann2013-04-08-0/+6
| | | | | | | | | | | | | | | | | | | | This patch adds the BCH result registers to register mapping for OMAP3 gpmc. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Reviewed-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-4/+27
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| * | exynos: change indentation of defines in cpu.hMinkyu Kang2013-04-04-3/+3
| | | | | | | | | | | | | | | | | | Fix the indentation of some defines by tab. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: clock: Add generic api to get the clk freqPadmavathi Venna2013-04-01-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: Add peripherial id for pwmPadmavathi Venna2013-04-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add peripherial id for pwm inorder to support generic api to get the clk frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: Add hardware accelerated SHA256 and SHA1Akshay Saraswat2013-03-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | video: exynos_dp: Remove callbacks from the driverAjay Kumar2013-03-27-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Replaced the functionality of callbacks by using a standard set of functions. Instead of implementing and hooking up a callback, put the same code in one of the standard set of functions by overriding it. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-0/+3
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| * | Add initial support for Wandboard dual lite and solo.Fabio Estevam2013-03-20-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | ARM: bcm2835: fix get_timer() to return msStephen Warren2013-04-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | ARM: mmu: Set domain permissions to client accessR Sricharan2013-03-28-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: mmu: Introduce weak dram_bank_setup functionR Sricharan2013-03-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a weak version of dram_bank_setup function to allow a platform specific function. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | ARM: cache: declare set_section_dcacheVincent Stehlé2013-03-28-0/+1
| |/ |/| | | | | | | | | | | | | | | We declare the set_section_dcache function globally in the cache header, for later use by e.g. machine specific code. Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com> Cc: Tom Rini <trini <at> ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-207/+130
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| * | Tegra114: Dalmore: Add SDIO3 pad config to pinctrl_config tableTom Warren2013-03-25-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | SDIO1 (the SD-card slot on Dalmore) needs to have its pads setup before the MMC driver is added. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra114: add SPI driverAllen Martin2013-03-25-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra114 SPI controller. This controller is not compatible with either the tegra20 or tegra30 controllers, so it requires a new driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | spi: add common fdt SPI driver interfaceAllen Martin2013-03-25-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a common interface to fdt based SPI drivers. Each driver is represented by a table entry in fdt_spi_drivers[]. If there are multiple SPI drivers in the table, the first driver to return success from spi_init() will be registered as the SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | tegra: spi: pull register structs out of headersAllen Martin2013-03-25-99/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move register structs from headers into .c files and use common name. This is in preparation of making common fdt front end for SPI drivers. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
generated by cgit v1.1 at 2024-11-01 05:39:03 +0000