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* armv8: ls2080: Change env variable "fdt_high"Saksham Jain2016-03-29-0/+7
| | | | | | | | | | "fdt_high" env variable was set to 0xcfffffff for secure boot. Change it to 0xa0000000 for LS2080 to be consistent with non-secure boot targets. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDRSaksham Jain2016-03-29-3/+25
| | | | | | | | | | | | | To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add bootscript header addr for secure bootSaksham Jain2016-03-29-0/+4
| | | | | | | | | | | | | | | | | | During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it executes. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from other ARM SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-29-2/+7
| | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-1/+6
| | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-29-0/+20
| | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-29-0/+7
| | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-0/+1
| | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci/layerscape: add defines for LUTStuart Yoder2016-03-21-0/+4
| | | | | | | | | | The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID. Add defines for the register offsets. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: update stream ID partitioning infoStuart Yoder2016-03-21-21/+34
| | | | | | | | | Update comments around how stream IDs are partitioned. Stream IDs allocated to PCI are no longer divided up by controller, but are instead a contiguous range Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPATAlison Wang2016-03-21-2/+2
| | | | | | | | | As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie2016-03-21-0/+4
| | | | | | | | | To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha2016-03-21-0/+2
| | | | | | | | | | Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon2016-03-15-3/+3
| | | | | | | | | | | | | | If EMIF is idle for certain amount of DDR cycles, EMIF will put the DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register is programmed. And also before entering suspend-resume ddr needs to be put in self-refresh. Linux kernel does not program this register before entering suspend and relies on u-boot setting. So configuring it in u-boot. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm64: Remove non-full-va map codeAlexander Graf2016-03-15-121/+53
| | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Move mmu table into board fileAlexander Graf2016-03-15-0/+2
| | | | | | | | | The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Make full va map code more dynamicAlexander Graf2016-03-15-45/+42
| | | | | | | | | | | | | | | | | | | The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-15-0/+1
| | | | | | | | | | | | When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-15-5/+1
| | | | | | | | Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf <agraf@suse.de>
* omap4: Reboot mode supportPaul Kocialkowski2016-03-15-0/+8
| | | | | | | | | | Reboot mode is written to SAR memory before reboot in the form of a string. This mechanism is supported on OMAP4 by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Properly enable USB PHY clocksPaul Kocialkowski2016-03-15-1/+4
| | | | | | | This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Rename set_muxconf_regs_essential to set_muxconf_regsPaul Kocialkowski2016-03-15-2/+2
| | | | | | | There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export jedec sdram timingsPaul Kocialkowski2016-03-15-1/+3
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the jedec timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram timingsPaul Kocialkowski2016-03-15-0/+5
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the elpidia timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram device detailsPaul Kocialkowski2016-03-15-0/+5
| | | | | | | | | Individual boards might provide their own emif_get_device_details function and use elpidia device details in their own way, hence those have to be exported. This also wraps existing definitions with the proper ifdef logic. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap3: Use a define for reboot reason offsetPaul Kocialkowski2016-03-15-0/+2
| | | | | | | | This introduces a define for the offset to the reboot reason, rather than hardcoding it. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: String-based reboot mode handlingPaul Kocialkowski2016-03-15-2/+2
| | | | | | | | This switches reboot mode handling to a string-based interface, that allows more flexibility to set a common interface with the next generations of OMAP devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-03-15-0/+98
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| * rockchip: video: Add LVDS support in vop driverJacob Chen2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | LVDS have a different display out mode, add code to get right flag. The vop_ip decide display device and the remote_vop_id decide which vop was being used. So we should use the remote_vop_id to set DCLK_VOP. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: video: Add a display driver for rockchip LVDSJacob Chen2016-03-14-0/+97
| | | | | | | | | | | | | | | | Some Rockchip SoCs support LVDS output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: DRA7: emif: Enable interleaving for higher address spaceLokesh Vutla2016-03-14-0/+3
| | | | | | | | | | | | | | | | Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Check for enable bits before updating leveling outputLokesh Vutla2016-03-14-0/+6
| | | | | | | | | | | | | | | | | | Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4/5: Add generic board detection hookKipisz, Steven2016-03-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many TI EVMs have capability to store relevant board information such as DDR description in EEPROM. Further many pad configuration variations can occur as part of revision changes in the platform. In-order to support these at runtime, we for a board detection hook which is available for override from board files that may desire to do so. NOTE: All TI EVMs are capable of detecting board information based on early clocks that are configured. However, in case of additional needs this can be achieved within the override logic from within the board file. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: omap-common: Add standard access for board description EEPROMLokesh Vutla2016-03-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several TI EVMs have EEPROM that can contain board description information such as revision, DDR definition, serial number, etc. In just about all cases, these EEPROM are on the I2C bus and provides us the opportunity to centralize the generic operations involved. The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM, AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format. However, DRA-7* EVMs, OMAP4SDP use a modified format. We hence introduce logic which is generic between these platforms without enforcing any specific format. This allows the boards to use the relevant format for operations that they might choose. This module will compile for all TI SoC based boards when CONFIG_TI_I2C_BOARD_DETECT is enabled to have optimal build times for platforms that require this support. It is important to note that this logic is fundamental to the board configuration process such as DDR configuration which is needed in SPL, hence cannot be part of the standard u-boot driver model (which is available later in the process). Hence, to aid efficiency, the eeprom contents are copied over to SRAM scratchpad memory area at the first invocation to retrieve data. To prevent churn with cases such as DRA7, where eeprom format maybe incompatible, we introduce a generic common format in eeprom which is made available over accessor functions for usage. Special handling for BBG1 EEPROM had to be introduced thanks to the weird eeprom rev contents used. The follow on patches introduce the use of this library for AM335x, AM437x, and AM57xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4/5: Centralize gpi2c_initKipisz, Steven2016-03-14-2/+3
| | | | | | | | | | | | | | | | | | | | Centralize gpi2c_init into omap_common from the sys_proto header so that the information can be reused across SoCs. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4/5: Centralize early clock initializationKipisz, Steven2016-03-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Early clock initialization is currently done in two stages for OMAP4/5 SoCs. The first stage is the initialization of console clocks and then we initialize basic clocks for functionality necessary for SoC initialization and basic board functionality. By splitting up prcm_init and centralizing this clock initialization, we setup the code for follow on patches that can do board specific initialization such as board detection which will depend on these basic clocks. As part of this change, since the early clock initialization is centralized, we no longer need to expose the console clock initialization. NOTE: we change the sequence slightly by initializing console clocks timer after the io settings are complete, but this is not expected to have any functioanlity impact since we setup the basic IO drive strength initialization as part of do_io_settings. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* | freescale: Remove CONFIG_DM from header filesSimon Glass2016-03-14-4/+0
|/ | | | | | | | | Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA. Remove the hacks which enable CONFIG_DM in header files and update the defconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
* colibri-vf: Disable pull-up configuration in GPIO pin muxBhuvanchandra DV2016-03-02-1/+1
| | | | | | | | | | | During very early boot-ROM execution the pinmux configuration isi in Hi-Z state. If pull-up is enabled on GPIO pad's there will be a short period of toggle from high to low on the IO when GPIO is set low during boot. To avoid this glitch, disable pull-up configuration in GPIO pinmux. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
* gpio: do not include <asm/arch/gpio.h> for UniPhierMasahiro Yamada2016-02-29-0/+2
| | | | | | | | | I implemented a GPIO driver based on Driver Model for the UniPhier SoC family, but I could not find any good reason why such SoC specific GPIO headers are needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-24-0/+4
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| * armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-24-0/+2
| | | | | | | | | | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu2016-02-24-0/+1
| | | | | | | | | | | | | | | | | | Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: enable workaround for errarum A009942Shengzhou Liu2016-02-24-0/+1
| | | | | | | | | | | | | | DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | stm32: add support for stm32f7 & stm32f746 discovery boardVikas Manocha2016-02-24-0/+346
| | | | | | | | | | | | This patch adds support for stm32f7 family & stm32f746 board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | gpio: stm32_gpio: move base addresses to the soc fileVikas Manocha2016-02-24-0/+18
| | | | | | | | | | | | | | Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | gpio: stm32_gpio: move clock config from driver to boardVikas Manocha2016-02-24-0/+11
| | | | | | | | | | | | | | This patch removes the gpio clock enable from gpio driver & move it in the board code, making it possible to use the gpio driver with other socs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-02-23-0/+30
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| * | sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-23-0/+30
| |/ | | | | | | | | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: zynq: Remove unused SPI base addressesMichal Simek2016-02-22-3/+0
|/ | | | | | | | Remove unused macros. Adresses are taken from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
generated by cgit v1.1 at 2024-11-08 11:38:23 +0000