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* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2014-05-20-1/+2
|\ | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
| * common/board_f: Initialized global data for generic boardYork Sun2014-05-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms (tested on mpc85xx, mpc86xx) use global data before calling function baord_inti_f(). The data should not be cleared later. Any arch which uses global data in generic board board_init_f() should define CONFIG_SYS_GENERIC_GLOBAL_DATA. Signed-off-by: York Sun <yorksun@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Simon Glass <sjg@chromium.org> CC: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
| * bd_info: remove bi_barudrate member from struct bd_infoMasahiro Yamada2014-05-12-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
* | Merge remote-tracking branch 'u-boot-sh/rmobile'Albert ARIBAUD2014-05-16-1222/+656
|\ \ | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Trivial conflict, maintainer change plus board addition
| * | arm: rmobile: Add register infomation of PLL regsiterNobuhiro Iwamatsu2014-04-28-0/+4
| | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: r8a7791: Add support ES2 revisionNobuhiro Iwamatsu2014-04-28-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | There is ES2 is a new revision to R8A7791. This adds support this revision. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: r8a7790: Add support ES2 revisionNobuhiro Iwamatsu2014-04-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | There is ES2 is a new revision to R8A7790. This adds support this revision. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add prototype for function to get the CPU information to rmobile.hNobuhiro Iwamatsu2014-04-28-0/+6
| | | | | | | | | | | | | | | | | | | | | These functions are defined but has no prototype declaration. Add them. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Coordinate the common part of the header file of r8a7790 and ↵Nobuhiro Iwamatsu2014-04-28-1224/+640
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r8a7791 Header files of R8A7790 and R8A7791 have common part of many. This coordinates as rcar-base.h. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-16-0/+208
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| * \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-05-15-0/+147
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| * | | imx25: Add new hardware registersThomas Diener2014-05-09-0/+175
| | | | | | | | | | | | | | | | Signed-off-by: Thomas Diener <dietho@gmx.de>
| * | | iomux-v3: Add support for mx6sl LVE bitFabio Estevam2014-05-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-04-29-2814/+2672
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| * | | mx6slevk: Add SPI NOR flash supportFabio Estevam2014-04-28-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6slevk has a m25p32 SPI NOR flash connected to ESCSPI port. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | | imx-common/video: add detect_hdmiEric Benard2014-04-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this function is used by several board together with board_video_skip to detect if hdmi is plugged is order to select the display to use. So move it in imx-common to share it. Signed-off-by: Eric Bénard <eric@eukrea.com>
| * | | imx-common: add board_video_skipEric Benard2014-04-15-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this function is shared by several boards and thus can be factorized Signed-off-by: Eric Bénard <eric@eukrea.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-16-0/+6
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| * | | | ARM: OMAP5: add CKO buffer control maskDmitry Lifshitz2014-05-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * | | | ARM: OMAP5: add UART4 supportDmitry Lifshitz2014-05-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add UART4 base address. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * | | | am33xx: add SSC enable macroYegor Yefremov2014-05-13-0/+2
| | |_|/ | |/| | | | | | | | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | | | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-15-2/+29
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| * | | | ARM: tegra: add function to enable input clamping on tristateStephen Warren2014-05-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HW-defined procedure for booting Tegra requires that CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux. Add a function to the pinmux driver to allow boards to do this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: add GPIO initialization table functionStephen Warren2014-05-13-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HW-defined procedure for booting Tegra requires that some pins be set up as GPIOs immediately at boot in order to avoid glitches on those pins, when the pinmux is programmed. Add a feature to the GPIO driver which executes a GPIO configuration table. Board files will use this to implement the correct HW initialization procedure. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: allow pinmux mux option not to be set by init tablesStephen Warren2014-05-13-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change the mux option in HW. For pins that will be used as GPIOs, the mux option is irrelevant, so we simply don't want to define any mux option in the pinmux initialization table. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | | ARM: tegra: set CONFIG_SYS_MMC_MAX_DEVICEStephen Warren2014-05-13-2/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_API is ever to be enabled on Tegra, this define must be set, since api/api_storage.c uses it. A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE 1) It isn't documented in README. The same is true for a lot of similar defines used by api_storage.c. 2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the valid values are 0..n-1 not 0..n. However, I this patch does not address those shortcomings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-15-437/+2289
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| * | | S5P: Exynos: Add GPIO pin numbering and rename definitionsAkshay Saraswat2014-05-13-437/+2289
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes following changes : * Adds gpio pin numbering support for EXYNOS SOCs. To have consistent 0..n-1 GPIO numbering the banks are divided into different parts where ever they have holes in them. * Rename GPIO definitions from GPIO_... to S5P_GPIO_... These changes were done to enable cmd_gpio for EXYNOS and cmd_gpio has GPIO_INPUT same as s5p_gpio driver and hence getting a error during compilation. * Adds support for name to gpio conversion in s5p_gpio to enable gpio command EXYNOS SoCs. Function has been added to asm/gpio.h to decode the input gpio name to gpio number. Example: SMDK5420 # gpio set gpa00 Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-0/+147
|\ \ \ | |/ / |/| | | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * | usb: ehci: rmobile: Add support ehci host driver of rmobile SoCsNobuhiro Iwamatsu2014-04-30-0/+147
| |/ | | | | | | | | | | | | | | The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-21-74/+1217
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| * | arm, da850: staticize funtionsManish Badarkhe2014-04-17-3/+0
| | | | | | | | | | | | | | | | | | | | | Make funtions static which are locally used in file and remove the declaration from header file. Signed-off-by: Manish Badarkhe <badarkhe.manish@gmail.com>
| * | keystone2: net: add keystone ethernet driverKaricheri, Muralidharan2014-04-17-0/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
| * | keystone2: add keystone multicore navigator driverVitaly Andrianov2014-04-17-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multicore navigator consists of Network Coprocessor (NetCP) and Queue Manager sub system. More details on the hardware can be obtained from the following links:- Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6 Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9 Multicore navigator driver implements APIs to configure the Queue Manager and NetCP Pkt DMA. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | k2hk: add support for k2hk SOC and EVMVitaly Andrianov2014-04-17-0/+777
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
| * | i2c, davinci: move i2c_defs.h to the drivers/i2c directoryKaricheri, Muralidharan2014-04-17-68/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the davinci i2c_defs.h file to drivers.i2c directory. It will allow to reuse the davinci_i2c driver for TI Keystone2 SOCs. Not used "git mv" command to move the file because small part of it with definitions specific for Davinci SOCs has to remain in the arch/arm/include/asm/arch-davinci. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | OMAP3: beagle-xm: generate fake USB ethernet MAC address from dieidNishanth Menon2014-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Similar to OMAP5uEVM, PandaBoard, BeagleBoard-XM has a USB based ethernet without MAC address embedded. So fake a MAC address following the similar strategy used on OMAP5 and PandaBoard family. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | omap3/sys_info: provide interface to read die idNishanth Menon2014-04-17-0/+1
| | | | | | | | | | | | | | | | | | | | | introduce get_die_id() function which allows generation of information such as fake MAC address from the processor ID code. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | OMAP: common: consolidate fake USB ethernet MAC address creationNishanth Menon2014-04-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI platforms such as OMAP5uevm, PandaBoard, use equivalent logic to generate fake USB MAC address from device unique DIE ID. Consolidate this to a generic location such that other TI platforms such as BeagleBoard-XM can also use the same. NOTE: at this point in time, I dont yet see a need for a generic dummy ethernet MAC address creation function, but if there is a need in the future, this can be further abstracted out. Signed-off-by: Nishanth Menon <nm@ti.com>
| * | ARM: OMAP: hide custom bit manipulation function sr32()Wolfgang Denk2014-04-17-3/+0
| |/ | | | | | | | | | | | | | | | | | | The only remaining user of the custom bit manipulation function sr32() is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in that file to prepare complete removal. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | ARM: tegra: pack pinmux data tables tighterStephen Warren2014-04-17-37/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: tegra: combine header fileStefan Agner2014-04-17-753/+225
| | | | | | | | | | | | | | | | | | | | | | Combine the Tegra USB header file into one header file for all SoCs. Use ifdef to account for the difference, especially Tegra20 is quite different from newer SoCs. This avoids duplication, mainly for Tegra30 and newer devices. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | usb: tegra: fix PHY configurationStefan Agner2014-04-17-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra30 and later, the PTS (parallel transceiver select) and STS (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register rather than PORTSC1_0 register. Since the reset configuration usually matches the intended configuration, this error did not show up on Tegra30 devices. Also use the slightly different bit fields of first USB, (USBD) on Tegra20 and move those definitions to the Tegra20 specific header file. Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-04-17-330/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-04-17-321/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Tegra30 pinmux cleanupStephen Warren2014-04-17-391/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra30_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted one entry in pinmux-config-cardhu.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-04-17-135/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: pinmux naming consistency fixesStephen Warren2014-04-17-56/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: reduce public pinmux APIStephen Warren2014-04-17-6/+0
| | | | | | | | | | | | | | | | | | | | | | Remove a few unused functions from the pinmux header. They aren't currently used, and removing them prevents any new usage from appearing. This will ease moving to just pinmux_config_table() and padgrp_config_table() in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: pinctrl: remove duplicationStephen Warren2014-04-17-698/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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