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* arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to KconfigYork Sun2016-10-06-7/+0
| | | | | | | Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to KconfigYork Sun2016-10-06-3/+0
| | | | | | | | Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move SYS_FSL_IFC_BANK_COUNT to KconfigYork Sun2016-10-06-3/+0
| | | | | | | | Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Move MAX_CPUS to KconfigYork Sun2016-10-06-5/+0
| | | | | | | | Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539Hou Zhiqiang2016-10-06-0/+2
| | | | | | | | | | | | | Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Fix "cpu status" commandYork Sun2016-10-06-0/+1
| | | | | | | | | | | | | | The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch2: enable snoopable sata read and writeTang Yuantian2016-10-06-0/+3
| | | | | | | | | | | | By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch2: adjust sata parameterTang Yuantian2016-10-06-2/+0
| | | | | | | | The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-10-03-3/+22
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| * rockchip: add boot-mode support for rk3288, rk3036Jacob Chen2016-10-01-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | rockchip platform have a protocol to pass the the kernel reboot mode to bootloader by some special registers when system reboot. In bootloader we should read it and take action. We can only setup boot_mode in board_late_init becasue "setenv" need env setuped. So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init" to replace "board_late_init" in board file. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rkpwm: fix the register sequenceKever Yang2016-10-01-1/+1
| | | | | | | | | | | | | | | | | | Reference to kernel source code, rockchip pwm has three type, we are using v2 for rk3288 and rk3399, so let's update the register to sync with pwm_data_v2 in kernel. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3399: update PPLL and pmu_pclk frequencyKever Yang2016-10-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz can not, 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost than 99MHz, 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using internally for kernel,it suppose not to change the bus clock like pmu_pclk in kernel, so we want to change it in uboot. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | arm: omap5: secure API for EMIF memory reservationsDaniel Allred2016-10-02-0/+24
|/ | | | | | | | | | | Create a few public APIs which rely on secure world ROM/HAL APIs for their implementation. These are intended to be used to reserve a portion of the EMIF memory and configure hardware firewalls around that region to prevent public code from manipulating or interfering with that memory. Signed-off-by: Daniel Allred <d-allred@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-09-30-1/+1
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/dra7xx_evm.h
| * dra7x: boot: add dfu bootmode supportB, Ravi2016-09-27-1/+1
| | | | | | | | | | | | | | | | This patch enables the DFU boot mode support for dra7x platform. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: tegra: add APIs the clock uclass driver will needStephen Warren2016-09-27-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: add peripheral clock init tableStephen Warren2016-09-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren2016-09-27-11/+0
| | | | | | | | | | | | | | | | | | | | | | Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | mmc: tegra: priv struct and naming cleanupStephen Warren2016-09-27-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren2016-09-27-2/+0
|/ | | | | | | | | | pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-14/+109
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDRYork Sun2016-09-26-2/+2
| | | | | | | | | | | | | | | | | | Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun2016-09-26-2/+0
| | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
| * armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2016-09-26-5/+3
| | | | | | | | | | | | | | | | | | Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-1/+2
| | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu2016-09-14-0/+6
| | | | | | | | | | | | | | | | | | Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | | | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add registers definition for system sleepHongbo Zhang2016-09-14-1/+53
| | | | | | | | | | | | | | | | This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: psci: make v7_flush_dcache_all public for all psci codeHongbo Zhang2016-09-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-9/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+11
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1043ardb: PPA: add PPA validation in case of secure bootSumit Garg2016-09-14-0/+18
| | | | | | | | | | | | | | | | | | | | As part of Secure Boot Chain of trust, PPA image must be validated before the image is started. The code for the same has been added. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-09-22-0/+336
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| * | rk3399: add a empty "sys_proto.h" header fileKever Yang2016-09-22-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a empty one to make compile success. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: use dummy byte only enable OF_PLATDATAXu Ziyuan2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a condition to determine the rk3288_sdram_channel size. This patch fixes read sdram_channel property failed from DT on rk3288 boards, which not enable OF_PLATDATA. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
| * | pinctrl: add driver for rk3399Kever Yang2016-09-22-0/+321
| | | | | | | | | | | | | | | | | | | | | This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rk3399: syscon: add support for pmugrfKever Yang2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | pmugrf is a module like grf which contain some of the iomux registers and other registers. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | ARM64: zynqmp: Add support for USB ulpi phy reset via mode pinsMichal Simek2016-09-22-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mode pins can be used as output for reset. Xilinx boards are using this feature as additional way how to reset USB phys and also others chips on the boards. Mode1 is used on all these boards for this feature. Let SPL toggle reset on this pin by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM: Add new BOOT_DEVICE_DFU boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | This enum is needed when SPL_DFU is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Add USB boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | Add USB boot mode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-09-22-0/+2
|/ / | | | | | | | | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini2016-09-18-1/+0
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| * | sunxi: musb: Power off OTG port VBUS when disabledChen-Yu Tsai2016-09-17-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel musb driver expects VBUS to be off while initializing musb. Having it on results in a repeating string of warnings, followed by an unusable peripheral. The peripheral is only usable after physically removing the OTG adapter, letting musb reset its state. This partially reverts commit c9f8947e6604 ("sunxi: usb-phy: Never power off the usb ports") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-07-16 18:14:13 +0000