summaryrefslogtreecommitdiff
path: root/arch/arm/include
Commit message (Collapse)AuthorAgeLines
* MLK-12495 mx6: Add LDO bypass supportYe Li2017-04-05-0/+10
| | | | | | | | | | | | | | | | Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
* MLK-14261-1 mx6solo: Rename the CONFIG_MX6SOLO to CONFIG_MX6SYe Li2017-04-05-1/+1
| | | | | | | | | | | | | Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes, we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO to CONFIG_MX6S. Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference for these two chips are core number and DDR controller. So all duallite relevant definitions can apply to solo. User can combine the two configs if any code only apply to solo or duallite. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2017-04-05-10/+52
| | | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> (cherry picked from commit f735f8ac328aa49759f6db524f7c2ba32622f711)
* MLK-12444-1 mfgtool: Add mfgtool supportYe Li2017-04-05-0/+7
| | | | | | | | | | | | | If boot from usb, reset environment to default value. Auto apply mfgtools setting and boot mfgtools kernel. Porting this from fsl uboot to uboot 2016. The 7dsabresd has already added the environment and usb boot related functions. No need to add them more. Only need to add NAND parts environment for mfgtools. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit a352ed3c5184b95c4c9f7468f5fbb5f43de5e412)
* MLK-12767 imx6ull: fix runtime checking for i.MX6ULLPeng Fan2017-04-05-3/+3
| | | | | | | | Fix runtime checking for i.MX6ULL. Add is_cpu_type(MXC_CPU_MX6ULL) to avoid using wrong code path. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 05922b0abf848949df778c19312cb1cf7fdfbe6a)
* MLK-12483-3 mx6: Add a module fuse checkingYe Li2017-04-05-0/+123
| | | | | | | | | | | | | | | | Implement a functionality to read the soc fuses and check if any module is fused. For fused module, we have to disable it in u-boot dynamically, and change the its node in FDT to "disabled" status before starting the kernel. In this patch, we implement the ft_system_setup for FDT fixup. This function will be called during boot process or by "fdt systemsetup" command. To enable the module fuse checking, two configurations must be defined: CONFIG_MODULE_FUSE CONFIG_OF_SYSTEM_SETUP Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 7236051526b73a5a25cc8330a79f5c08b7d70726)
* MLK-10496: Check the PL310 version for applying errataNitin Garg2017-04-05-0/+7
| | | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
* ENGR00325255 pcie:enable pcie support on imx6sx sdYe Li2017-04-05-0/+3
| | | | | | | | | | | | | | | | | Enable pcie support in uboot on imx6sx sd boards - enable_pcie_clock should be call before ssp_en is set, since that ssp_en control the phy_ref clk gate, turn on it after the source of the pcie clks are stable. - add debug info - add rx_eq of gpr12 on imx6sx - there are random link down issue on imx6sx. It's pcie ep reset issue. solution:reset ep, then retry link can fix it. (cherry picked from commit ec78595a24b5ff1020baa97b6d6e79a3a3326307) Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 81fd30250110d72992758f08b66c07306126892b)
* ENGR00315894-77 mx6 soc: Add vadc power up/down functionYe.Li2017-04-05-0/+3
| | | | | | | | | | | Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 96d990ef754a879f6ca9da4adf6e0be3d21cdc51) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 01b88201aa86bef26a4254ac43aff90e99fd2c06) (cherry picked from commit d50b53f138dd3b4c463c80ac8e14f41ac0fdd415)
* ENGR00315894-76 mx6 clock: Add vadc clock enable functionYe.Li2017-04-05-0/+1
| | | | | | | | | | | Add vadc clock enable function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 721c7a1448c5b7265b597b83d18f8338a27ea213) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 903a59ef941f39b6d7f693dd7c60528e166de079) (cherry picked from commit dc767fb7d5c155f2a6ef01c4dee808b9c1944fc2)
* MLK-12437-3 mx6sxsabresd: Update display to support panel selectionYe Li2017-04-05-0/+2
| | | | | | | | Support two display panels, one for LVDS, another for parallel LCD. Align the feature to the v2015.04 uboot. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit d7f54f22607ffcace6cda97984649a5ae4f65996)
* MLK-12437-2 Video: Update the common board_video_skip to support MXS LCDYe Li2017-04-05-0/+6
| | | | | | | Update the board_video_skip to use CONFIG_VIDEO_MXS for LCD display support. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit d6d0265b09e66c576ab4c01841166415f834a1ff)
* MLK-12437-1 mx6sx: Add support for LVDS displayYe Li2017-04-05-0/+3
| | | | | | | | The i.MX6SX uses a LVDS bridge to mux to the LCDIF interface. Implmement a function for this muxing. So that on 6SX we can use a LVDS display. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 763658d9b497e44b7411581da592ef5b522e9cc9)
* MLK-12434-1: imx: dynamic setting mmcdev and mmcrootPeng Fan2017-04-05-0/+5
| | | | | | | | Align to imx_v2015.04, dynamic setting mmcdev and mmcroot. Then when boot linux, we can have correct "root=/dev/mmcblk[x]p2" Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit b46b99a901eb194e81fc4836ee2259ad8857f4d3)
* MLK-12425-1: mx6sl/ul: introudce more pinmux macrosPeng Fan2017-04-05-3/+84
| | | | | | | Introuduce more pinmux macros definitions. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 06893558f2cc042b683247989be5127a8027ebf2)
* MLK-12693-2 nand: mxs: correct bitflip for erased NAND pagePeng Fan2017-04-05-1/+5
| | | | | | | | | | | | | | | | | | | | This patch is a porting of http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38 " i.MX6QP and i.MX7D BCH module integrated a new feature to detect the bitflip number for erased NAND page. So for these two platform, set the erase threshold to gf/2 and if bitflip detected, GPMI driver will correct the data to all 0xFF. Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q with the one for i.MX6QP. " In this patch, i.MX6UL is added and threshold changed to use ecc_strength. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0) Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2017-03-14-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 29b9bdbbdac9678dba9b7bc2d3662598e9c548a5) (cherry picked from commit 6d45292ff7e7020a48842f033f8a337daabe4476)
* MLK-12416-4: imx: mx6: update imx-regs.hPeng Fan2017-03-14-13/+119
| | | | | | | Update imx-regs.h to align with 2016.03 Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9bbd54e44ae1f0868d3f0dd34975e76606b0a5e8)
* arm: OMAP2+: nandecc: propagate error to command return statusLadislav Michl2017-03-11-2/+2
| | | | | | | | | Currently nandecc returns zero even if underlaying omap_nand_switch_ecc function fails. Fix that by propagating error returned to command return value. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: Migrate errata to KconfigTom Rini2017-03-09-6/+0
| | | | | | | | | This moves all of the current ARM errata from various header files and in to Kconfig. This allows for a minor amount of cleanup as we had some instances where both a general common header file was enabling errata as well as the board config. We now just select these once at the higher level in Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* Freescale/NXP: Migrate CONFIG_FSL_CAAM to defconfigsTom Rini2017-03-09-5/+0
| | | | | | | | | | | | | | | | | | | | | | In some cases this is absolutely required, so select this for some secure features. This also requires migration of RSA_FREESCALE_EXP Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Saksham Jain <saksham.jain@nxp.freescale.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv5te: make 'ret lr' produce iinterworking 'bx lr'Albert ARIBAUD2017-03-01-1/+1
| | | | | | | | | | | | | | | | | Current ARM assembler helper for the 'return to caller' pseudo-instruction turns 'ret lr' into 'mov pc, lr' for ARMv5TE. This causes the core to remain in its current ARM state even when the routine doing the 'ret' was called from Thumb-1 state, triggering an undefined instruction exception. This causes early run-time failures in all boards compiled using the Thumb-1 instruction set (for instance the Open-RD family). ARMv5TE supports 'bx lr' which properly implements interworking and thus correctly returns to Thumb-1 state from ARM state. This change makes 'ret lr' turn into 'bx lr' for ARMv5TE. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* ARM: DRA7xx: Fix memory allocation overflowAndrew F. Davis2017-02-17-1/+1
| | | | | | | | | | When using early malloc the allocated memory can overflow into the SRAM scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more dynamic allocation at the expense of a slightly smaller maximum image size. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-02-01-0/+16
|\ \
| * | ARM: imx6ul: Move liteSOM source to SoC directoryMarcin Niestroj2017-01-27-0/+16
| |/ | | | | | | | | | | | | | | | | | | | | Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz2017-01-28-2/+5
| | | | | | | | | | | | This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
* | net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-0/+39
| | | | | | | | | | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: stm32: use clock setup function defined in clock.cMichael Kurz2017-01-28-26/+3
| | | | | | | | | | | | | | | | | | | | | | Use the clock setup function defined in clock.c instead of setting the clock bits directly in the drivers. Remove register definitions of RCC in rcc.h as these are already defined in the struct in stm32.h Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: fix stm32f7 sdram fmc base addressMichael Kurz2017-01-28-3/+2
| | | | | | | | | | | | | | | | | | The fmc base address is defined twice, once in fmc.h and once in stm32.h. Fix wrong definition in stm32.h. Remove the definiton in fmc.h. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: cleanup stm32f7 filesMichael Kurz2017-01-28-28/+46
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
* | arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703Adam Ford2017-01-28-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but anything else is lumped into 36XX/37XX with an assumed 1GHz speed. Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ). This also adds the ability to distinguish between the DM3730, DM3725, AM3715, and AM3703 and correctly display their maximum speed. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* | ARM: am335x: Add support for chiliSOMMarcin Niestroj2017-01-28-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * TI AM335x processor * 128M, 256M or 512M DDR3 memory * up to 256M NAND We place source inside arch/arm/mach-omap2/ directory and make it possible to reuse initialization code (i.e. DDR, NAND init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com2017-01-28-0/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: Re-sync with full list of MACH_TYPE_xxx valuesTom Rini2017-01-28-1/+4064
| | | | | | | | | | | | | | This re-syncs us with the official and full list of MACH_TYPE_xxx values from http://www.armlinux.org.uk/developer/machines/ Signed-off-by: Tom Rini <trini@konsulko.com>
* | disk: convert CONFIG_DOS_PARTITION to KconfigPatrick Delaunay2017-01-28-2/+0
|/ | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* config: Drop CONFIG_ARCH_DMA_PIO_WORDSSimon Glass2017-01-25-6/+1
| | | | | | This is not defined by any board in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini2017-01-24-8/+0
| | | | | | | | | Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* config: Move CONFIG_BOARD_LATE_INIT to defconfigsJagan Teki2017-01-21-1/+0
| | | | | Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-01-19-30/+62
|\
| * ARMv8/sec_firmware: relocated and renamed the config FSL_PPA_ARMV8_PSCIHou Zhiqiang2017-01-18-1/+1
| | | | | | | | | | | | | | | | Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: aarch64: Fix the warning about x1-x3 nonzero issueAlison Wang2017-01-18-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | For 64-bit kernel, there is a warning about x1-x3 nonzero in violation of boot protocol. To fix this issue, input argument 4 is added for armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will be set to the right value, such as zero. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/ls1043a: fixup GIC offset for ls1043a rev1Wenbin Song2017-01-18-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose which offset will be used. The LS1043A rev1.0 silicon only supports the CIG offset with 4K alignment. If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment is used. 64K alignment is the default setting. Overriding the weak smp_kick_all_cpus, the new impletment is able to detect GIC offset. The default GIC offset in kernel device tree is using 4K alignment, it need to be fixed if 64K alignment is detected. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add chip power supply voltage setupHou Zhiqiang2017-01-18-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set up chip power supply voltage according to voltage ID. The fuse status register provides the values from on-chip voltage ID fuses programmed at the factory. These values define the voltage requirements for the chip. Main operations: 1. Set up the core voltage 2. Set up the SERDES voltage and reset SERDES lanes 3. Enable/disable DDR controller support 0.9V if needed Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE_BOOT: Update bootscript and its hdr addressesUdit Agarwal2017-01-18-6/+6
| | | | | | | | | | | | | | | | | | Update bootscript and its hdr addresses for Layerscape Chasis 3 based platforms instead of individual SoCs. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-lsch3: consolidate the clock system initializationHou Zhiqiang2017-01-18-0/+1
| | | | | | | | | | | | | | | | This patch binds the sys_info->freq_systembus to Platform PLL, and implements the IPs' clock function individually. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-lsch2: refactor the clock system initializationHou Zhiqiang2017-01-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Add the OCRAM initializationHou Zhiqiang2017-01-18-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear the content to zero and the ECC error bit of OCRAM1/2. The OCRAM must be initialized to ZERO by the unit of 8-Byte before accessing it, or else it will generate ECC error. And the IBR has accessed the OCRAM before this initialization, so the ECC error status bit should to be cleared. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-08-21 00:38:35 +0000