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* ehci-mxc: Add support for i.MX35Benoît Thébaudeau2012-11-16-0/+2
| | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ehci-mxc: Define host offsetsBenoît Thébaudeau2012-11-16-0/+2
| | | | | | | | | | Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at SoC level. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* mx31: Move EHCI definitions to ehci-fsl.hBenoît Thébaudeau2012-11-16-26/+0
| | | | | | | | | The EHCI definitions in i.MX31's imx-regs.h are MXC-generic, so move them to ehci-fsl.h so that all MXC SoCs can use them. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* arch-mx6: add mx6dl_pins.hTroy Kisky2012-11-10-0/+149
| | | | | | | Only the values used in the sabrelite board are added currently. Add more as other boards use them. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* imx-common: cpu: add imx_ddr_sizeTroy Kisky2012-11-10-0/+2
| | | | | | | | | | Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky2012-11-10-2/+18
| | | | | | | | | | Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* Merge git://git.denx.de/u-bootStefano Babic2012-11-10-1932/+333
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| * Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-11-03-0/+5
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| | * arm bootm: Allow to pass board specified atagsPali Rohár2012-10-30-0/+5
| | | | | | | | | | | | | | | | | | Board can implement function setup_board_tags which is used for adding atags Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
| * | tegra: move to common SPL frameworkAllen Martin2012-10-29-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change tegra SPL to use common SPL framework. Any tegra specific initialization is now done in spl_board_init() instead of board_init_f()/board_init_r(). Only one SPL boot target is supported on tegra, which is boot to RAM image. jump_to_image_no_args() must be overridden on tegra so the host CPU can be initialized. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2012-10-27-130/+1195
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| * | | arm: Remove support for NETARMMarek Vasut2012-10-26-1279/+1
| | | | | | | | | | | | | | | | | | | | | | | | This stuff has been rotting in the tree for a while now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | | arm: Remove support for s3c4510Marek Vasut2012-10-26-272/+0
| | | | | | | | | | | | | | | | | | | | | | | | This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | | arm: Remove support for lpc2292Marek Vasut2012-10-26-340/+0
| | | | | | | | | | | | | | | | | | | | | | | | This stuff has been rotting in the tree for a year now. Remove it. Signed-off-by: Marek Vasut <marex@denx.de>
| * | | Merge remote-tracking branch 'u-boot-ti/master'Albert ARIBAUD2012-10-26-60/+318
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| | * | am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbersPeter Korsgaard2012-10-25-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | So other parts can be added. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| | * | am33xx: support board specific ddr settingsPeter Korsgaard2012-10-25-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the hardcoded ddr2/ddr3 settings for the ti boards to board code, so other boards can use different types/timings. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make apply with rtc32k_enable() in the file] Signed-off-by: Tom Rini <trini@ti.com>
| | * | am33xx: move generic parts of pinmux handling out from board/ti/am335xPeter Korsgaard2012-10-25-0/+261
| | | | | | | | | | | | | | | | | | | | | | | | So they are available for other boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
| | * | am33xx: move ti i2c baseboard header handling to board/ti/am335x/Peter Korsgaard2012-10-25-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini <trini@ti.com>
| | * | am33xx: Add SPI SPL as an optionTom Rini2012-10-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the required config.mk logic for this SoC as well as the BOOT_DEVICE define. Finally, enable the options on the am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| | * | VIDEO: add macro to set LCD size for DSS driverStefano Babic2012-10-25-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| | * | am335x: Enable RTC 32K OSC clockVaibhav Hiremath2012-10-25-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support low power state, you must source kernel system timers to persistent clock, available across suspend/resume. In case of AM335x device, the only source we have is, RTC32K, available in wakeup/always-on domain. Having said that, during validation it has been observed that, RTC clock need couple of seconds delay to stabilize the RTC OSC clock; and such a huge delay is not acceptable in kernel especially during early init and also it will impact quick/fast boot use-cases. So, RTC32k OSC enable dependency has been shifted to SPL/first-bootloader. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | | arm: Change global data baudrate to intSimon Glass2012-10-19-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This does not need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | | mx25: Place common functions into sys_proto.hFabio Estevam2012-10-26-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | imx-regs.h is meant to contain SoC register definitions. Common SoC funtions should go to sys_proto.h instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | MX35: add support for woodburn boardStefano Babic2012-10-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The woodburn board is based on the MX35 SOC. Support for both external (NOR) and internal (SD Card) boot mode are added. It uses the generic SPL framework to implement the internal boot mode. The following peripherals are supported: - Ethernet (FEC) - SD Card - NAND (512 MB) - NOR Flash In the internal boot mode, a simple imximage header is generated to set the address in internal RAM where the SOC must copy the SPL code. The initial setup is then demanded to the SPL itself. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | MX35: Add soc_boot_mode and soc_boot_device to MX35Stefano Babic2012-10-26-0/+69
| | | | | | | | | | | | | | | | | | | | | The functions are required to use the generic SPL Framework. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | | MX35: add LOW_LEVEL_SRAM_STACK to use SPL_FRAMEWORKStefano Babic2012-10-26-0/+2
| |/ |/| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* | mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-17-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx25: Clean up imx-regs.hBenoît Thébaudeau2012-10-16-3/+3
| | | | | | | | | | | | | | | | | | | | Clean up i.MX25 imx-regs.h: - Update mx31 imx-regs.h filename. - Test for __KERNEL_STRICT_NAMES just in case. - Define internal RAM size. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* | i.MX6: add HDMI transmitter register declarations from kernel WIP.Eric Nelson2012-10-16-0/+1053
| | | | | | | | | | | | | | | | Original source from Pengutronix HDMI driver work: http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commitdiff;h=72c31cd67ac880bd90785af86f8e46f8ea7b3bb0 Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX6: set drive strength for parallel RGB padsEric Nelson2012-10-16-29/+29
| | | | | | | | | | | | Default drive strength is disabled and won't function. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | i.MX: iomux: input pad array can be constEric Nelson2012-10-16-1/+2
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
* | mx6qsabreauto: Pass the board revision to the kernelFabio Estevam2012-10-16-0/+6
| | | | | | | | | | | | | | | | | | | | | | The kernel from Freescale expects that the bootloader passes the board revision. Read the board revision and pass it via get_board_rev(). Without passing the board revision the kernel does not operate properly as the initialization of peripherals are different in revA versus revB boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | mx35: Fix eSDHC clocksBenoît Thébaudeau2012-10-16-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Each eSDHC instance has a dedicated clock. gd->sdhc_clk must also be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* | mx35: Clean up lowlevel_initBenoît Thébaudeau2012-10-16-96/+95
|/ | | | | | | | | | | | Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. - Use macro parameters with default values instead of #define'd configs. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx25: Clean up lowlevel_initBenoît Thébaudeau2012-10-15-22/+65
| | | | | | | | | | | | | | | Clean up mx25 lowlevel_init: - Add comments. - Do not use write32 repeatedly with the same value in order not to increase code size. - Make register values configurable. - Use macro parameters with default values instead of literal constants. - Use defined macros instead of duplicating code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Matthias Weisser <weisserm@arcor.de>
* mx31: Fix PDR0_CSI_PODFBenoît Thébaudeau2012-10-15-2/+4
| | | | | | | | | | The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx35: Define MAX and AIPS registersBenoît Thébaudeau2012-10-15-0/+52
| | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx31: Add more CCM access macrosBenoît Thébaudeau2012-10-15-0/+10
| | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx25: Clean up clocks APIBenoît Thébaudeau2012-10-15-6/+3
| | | | | | | | Use the standard mxc_get_clock() instead of exporting internal functions and using literal constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx25 clocks: Fix MXC_FEC_CLKBenoît Thébaudeau2012-10-15-1/+1
| | | | | | | | | | mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock. Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG clock, so remove the duplicated code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx25: Define more standard clocksBenoît Thébaudeau2012-10-15-0/+5
| | | | | | | Define AHB, IPG and CSPI clocks. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-15-0/+4
| | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* mx5 clocks: Fix get_lp_apm()Benoît Thébaudeau2012-10-15-0/+15
| | | | | | | | | | | | If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Add and use CCSR definitionsBenoît Thébaudeau2012-10-15-0/+23
| | | | | | | This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-1/+2
| | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* mx5: Fix clock gate valuesBenoît Thébaudeau2012-10-15-0/+3
| | | | | | | | | The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-4/+275
| | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: CleanupBenoît Thébaudeau2012-10-15-6/+93
| | | | | | | | | | Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-0/+28
| | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
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