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* arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-12-1/+1
| | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-12/+25
|\ | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-5/+16
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| | * am335x: fix GPMC config for NAND and NOR SPL bootpekon gupta2013-11-21-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * mtd: nand: omap: enable BCH ECC scheme using ELM for generic platformpekon gupta2013-11-21-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta <pekon@ti.com> [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | i2c, omap24xx: convert driver to new mutlibus/mutliadapter frameworkHeiko Schocher2013-11-13-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Tom Rini <trini@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Thomas Weber <weber@corscience.de> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Nishanth Menon <nm@ti.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Michael Jones <michael.jones@matrix-vision.de> Cc: Raphael Assenat <raph@8d.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefano Babic <sbabic@denx.de>
| * omap3_dss: define DSS_ONOFFNikita Kiryanov2013-11-12-4/+5
| | | | | | | | | | | | | | | | | | | | | | Add DSS_ONOFF to polarity defines Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Anatolij Gustschin <agust@denx.de>
| * ARM: bcm2835: add missing mbox overscan response fieldAndre Heider2013-11-12-0/+1
| | | | | | | | | | | | | | | | Add the missing "right" field to struct bcm2835_mbox_tag_overscan. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | at91: redefine legacy GPIO PIN_BASEAndreas Bießmann2013-12-09-1/+1
| | | | | | | | | | | | | | In order to get the very same value for legacy pin definitions and new gpio definitions set the legacy PIN_BASE to 0. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: add new gpio pin definitionsAndreas Bießmann2013-12-09-1/+23
| | | | | | | | | | | | | | | | This patch define new names for GPIO pins on at91 devices. Follow up patches will convert the whole infrastructure to use these new definitions. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-7/+4
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| * | arm: exynos: remove the unused define.Jaehoon Chung2013-12-05-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | These defines didn't use anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos/goni: fix the return type for s5p_mmc_initJaehoon Chung2013-12-05-2/+2
| | | | | | | | | | | | | | | | | | | | | The "int" type is right. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: spl: Add a custom spi copy functionRajeshwari Shinde2013-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: fix the align for exynos4_power structureMinkyu Kang2013-12-03-1/+1
| |/ | | | | | | | | | | | | res3 should be 4bytes Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dominik Klein <dominik.klein@gmx.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-30/+96
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| * | arm: omap3: Enable clocks for peripherals only if they are usedMichael Trimarchi2013-12-06-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel2013-12-04-0/+4
| | | | | | | | | | | | Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
| * | davinci: fix Master Priority Registers locationViktar Palstsiuk2013-12-04-1/+2
| | | | | | | | | | | | | | | | | | | | | MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@promwad.com>
| * | arm: omap3: Add uart4 omap3 adddressMichael Trimarchi2013-12-04-0/+1
| | | | | | | | | | | | | | | | | | This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
| * | ARM: OMAP5: Add SATA platform glueRoger Quadros2013-12-04-0/+48
| | | | | | | | | | | | | | | | | | Add platform glue logic for the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros2013-12-04-0/+8
| | | | | | | | | | | | | | | | | | | | | Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039SRICHARAN R2013-12-04-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: DRA: EMIF: Change DDR3 settings to use hw levelingSRICHARAN R2013-12-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: DRA7: Add is_dra7xx cpu check definitionSRICHARAN R2013-12-04-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra7xx cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | am33xx: Stop modifying certain EMIF4D registersTom Rini2013-12-04-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
| * | cm_t335: add cm_t335 board supportIlya Ledvich2013-12-04-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add cm_t335 board directory, config file. Enable build. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> [trini: Adapt Makefile] Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-0/+2113
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| * | arm: rmobile: Add support koelsch boardNobuhiro Iwamatsu2013-12-03-3/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB, Quad SPI, Ethernet, and more. This patch supports the following functions: - DDR3-SDRAM - SCIF Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
| * | arm: rmobile: Add support R8A7791Nobuhiro Iwamatsu2013-12-03-0/+1041
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas R8A7791 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
| * | arm: rmobile: Add support R8A7790Nobuhiro Iwamatsu2013-12-03-0/+1006
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas R8A7790 is CPU with Cortex-A7 and A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
* | | socfpga: Adding Freeze Controller driverChin Liang See2013-12-03-0/+50
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Adding Freeze Controller driver. All HPS IOs need to be in freeze state during pin mux or IO buffer configuration. It is to avoid any glitch which might happen during the configuration from propagating to external devices. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | arm926ejs, at91: add common phy_reset functionHeiko Schocher2013-12-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add common phy reset code into a common function. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Jens Scharsig <esw@bus-elektronik.de> Cc: Sergey Lapin <slapin@ossfans.org> Cc: Stelian Pop <stelian@popies.net> Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com> Cc: Eric Benard <eric@eukrea.com> Cc: Markus Hubig <mhubig@imko.de> Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Tested-by: Bo Shen <voice.shen@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: atmel: sama5d3: spl boot from fat fs SD cardBo Shen2013-12-01-0/+24
| | | | | | | | | | | | | | | | Enable Atmel sama5d3xek boart spl boot support, which can load u-boot from SD card with FAT file system. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: atmel: add ddr2 initialization functionBo Shen2013-12-01-0/+115
| | | | | | | | | | | | | | | | The MPDDRC supports different type of SDRAM This patch add ddr2 initialization function Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: atmel: sama5d3: the offset of MULA is 18Bo Shen2013-12-01-0/+4
| | | | | | | | | | | | | | | | The offset of MULA field in PLLA register in sama5d3 is 18, and the length only 7 bits. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: atmel: sama5d3: correct the error define of DIVBo Shen2013-12-01-2/+2
| | | | | | | | | | | | | | Correct the error define of DIV. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: at91: sama5d3: add support for sama5d36 chipWu, Josh2013-11-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | The SAMA5D36 chip is the superset product of SAMA5D3x family. For detail information please refer to: http://www.atmel.com/Microsite/sama5d3/default.aspx Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: remove all occourances of CONFIG_AT91_LEGACYAndreas Bießmann2013-11-13-246/+6
|/ | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-61/+67
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-07-12/+3
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| | * mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pinOtavio Salvador2013-10-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4 pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12 mainline kernel. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * ARM: mxs: Setup stack in JTAG modeMarek Vasut2013-10-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the MX23/MX28 is switched into JTAG mode via the BootMode select switches, the BootROM bypasses the CPU core registers initialization. This in turn means that the Stack Pointer (SP) register is not set as it is in every other mode of operation, but instead is only zeroed out. To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out. Note that in case the SP is already configured, we must preserve that exact SP value and must not modify it. This is important since in every other mode but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to continue it's operation after returned from SPL and the system would crash. Finally, add the JTAG mode switch identifier, so it's not recognised as Unknown mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6: compute PLL PFD frequencies rather than using definesPierre Aubert2013-10-17-11/+0
| | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
| * | Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-05-0/+9
| |\ \
| | * | at91: add defines for reset typeRoger Meier2013-11-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Roger Meier <r.meier@siemens.com> Acked-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | arm: atmel: at91sam9n12ek: add usb host supportBo Shen2013-11-04-0/+2
| | |/ | | | | | | | | | | | | | | | | | | Add usb host support for at91sam9n12ek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: OMAP5: DDR3: Change io settingsSRICHARAN R2013-11-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change from 0x64656465 to 0x64646464 is to remove the weak pull enabled on DQS, nDQS lines. This pulls the differential signals in the same direction which is not intended. So disabling the weak pulls improves signal integrity. On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being supplied a VREF! This was clearly a mistake. The second change improves the robustness of the interface and was specifically seen to cure corruption observed at high temperatures on some boards. With the above two changes better memory stability was observed with extended temperature ranges around 100C. Signed-off-by: Sricharan R <r.sricharan@ti.com>
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