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| * imx: add i.MX 6SLL CPU typePeng Fan2016-12-16-1/+3
| | | | | | | | | | | | | | | | Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | ARMv8: Setup PSCI memory and device treemacro.wave.z@gmail.com2016-12-15-1/+12
| | | | | | | | | | | | | | | | | | Newly add ARMv8 PSCI needs to be initialized, be copied or reserved in right place, this patch does all the setup steps. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: Add basic PSCI frameworkmacro.wave.z@gmail.com2016-12-15-0/+15
| | | | | | | | | | | | | | | | | | | | This patch introduces a generic ARMv8 PSCI framework, with all functions returning a dummy ARM_PSCI_RET_NI (Not Implemented), then it is up to each platform to implement their own functions based on this framework. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: Enable SMC instructionmacro.wave.z@gmail.com2016-12-15-1/+7
| | | | | | | | | | | | | | | | PSCI implementation needs the SMC instruction to be enabled. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definitionmacro.wave.z@gmail.com2016-12-15-1/+1
|/ | | | | | | | | | | | NXP/Freescale uses macro CONFIG_ARMV8_PSCI to enable their private PSCI implementation in PPA firmware, but this macro naming too generic, so this patch replaces it with a specic one CONFIG_FSL_PPA_ARMV8_PSCI. And this macro CONFIG_ARMV8_PSCI will be used for a generic PSCI for ARMv8 which will be added in following patchs. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-12-12-0/+38
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| * arm64: mvebu: Add L3 cache flush functionality to A8K familyKonstantin Porotchkin2016-12-12-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: pinctrl: Add pin control driver for A8K familyKonstantin Porotchkin2016-12-12-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: am33xx: Initialize EMIF REG_PR_OLD_COUNT for BBB and am335x-evmJyri Sarha2016-12-09-0/+1
|/ | | | | | | | | | | | | | Initialize EMIF OCP_CONFIG registers REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT field for Beaglebone-Black and am335x-evm. With the default values LCDC suffers from DMA FIFO underflows and frame synchronization lost errors. The initialization values are the highest that work flawlessly when heavy memory load is generated by CPU. 32bpp colors were used in the test. On BBB the video mode used 110MHz pixel clock. The mode supported by the panel of am335x-evm uses 30MHz pixel clock. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Revert "Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze"Tom Rini2016-12-09-0/+2
| | | | | This reverts commit 3edc0c252257e4afed163a3a74aba24a5509b198, reversing changes made to bb135a0180c31fbd7456021fb9700b49bba7f533.
* block: Move ceva driver to DMMichal Simek2016-12-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Series-to: sjg, agraf@suse.de Series-cc: uboot Series-version: 4 Series-changes: 2 - make ceva_init_sata static - Move SATA_CEVA to defconfig - Initalized max_lun and max_id platdata Series-changes: 3 - Extend Kconfig help description - sort dm.h - Remove SPL undefinition from board file - Fix Kconfig dependecies
* armv8: QSPI: Add AHB bus 16MB+ size supportYuan Yao2016-12-05-0/+2
| | | | | | | | The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-04-3/+2
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| * script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white listYork Sun2016-12-02-3/+2
| | | | | | | | | | | | | | Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com>
* | board: ti: am572x: Add pinmux for X15/GPEVM SR2.0 using latest PMTNishanth Menon2016-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the board pinmux for AM572x-IDK board using latest PMT[1] and the board files named am572x_gp_evm_A3a_sr2p0 that were autogenerated on 19th October, 2016 by "Ahmad Rashed<a-rashed@ti.com>". [1] https://dev.ti.com/pinmux/app.html#/default/ Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4+: Add support for getting pbias info from boardLokesh Vutla2016-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based boards to enable mmc regulator. This is not true always like in case of DRA71x-evm. So get this information based on the board. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | board: ti: dra71x-evm: Add PMIC supportKeerthy2016-12-04-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Redefine voltage and efuse macros per OPP using KconfigSuman Anna2016-12-04-13/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Redefine the macros used to define the voltage values and the efuse register offsets based on OPP for all the voltage domains. This is done using Kconfig macros that can be set in a defconfig or selected during a config step. This allows a voltage domain to be configured/set to a corresponding voltage value depending on the OPP selection choice. The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU voltage domains, with the MPU domain restricted to OPP_NOM. The OPP_OD and OPP_HIGH options will be added when the support for configuring the MPU clock frequency is added. The clock configuration for other voltage domains is out of scope in u-boot code. The CORE voltage domain does not have separate voltage values and efuse register offset at different OPPs, while the MPU voltage domain only has different efuse register offsets for different OPPs, but uses the same voltage value. Any different choices of OPPs for voltage domains on common ganged-rails is automatically taken care to select the corresponding highest OPP voltage value. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4+: Add support for dynamically selecting OPPsLokesh Vutla2016-12-04-2/+21
| | | | | | | | | | | | | | | | | | | | | | It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-dmTom Rini2016-12-03-6/+7
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| * | drivers: usb: musb: adopt musb backend driver to driver modelMugunthan V N2016-12-02-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all backend driver ops uses hard coded physical address, so to adopt the driver to DM, add device pointer to ops call backs so that drivers can get physical addresses from the usb driver priv/plat data. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap5: Add TEE loading supportHarinarayan Bhatta2016-12-03-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | secure_tee_install is used to install and initialize a secure TEE OS such as Linaro OP-TEE into the secure world. This function takes in the address where the signed TEE image is loaded as an argument. The signed TEE image consists of a header (struct tee_header), TEE code+data followed by the signature generated using image signing tool from TI security development package (SECDEV). Refer to README.ti-secure for more information. This function uses 2 new secure APIs. 1. PPA_SERV_HAL_TEE_LOAD_MASTER - Must be called on CPU Core 0. Protected memory for TEE must be reserved before calling this function. This API needs arguments filled into struct ppa_tee_load_info. The TEE image is authenticated and if there are no errors, the control passes to the TEE entry point. 2. PPA_SERV_HAL_TEE_LOAD_SLAVE - Called on other CPU cores only after a TEE_LOAD_MASTER call. Takes no arguments. Checks if TEE was successfully loaded (on core 0) and transfers control to the same TEE entry point. The code at TEE entry point is expected perform OS initialization steps and return back to non-secure world (U-Boot). Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap5: Add function to make an SMC call on cpu1Harinarayan Bhatta2016-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some cases it is need to make secure API calls from Core 1. This patch adds an assembly function to make a secure (SMC) call from CPU Core #1. Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XXNishanth Menon2016-12-03-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_AM57XX is just an unnecessary macro that is redundant given So, remove the same instead of spreading through out the u-boot source code and getting in the way to maintain common code for DRA7x family. Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+3
|/ / | | | | | | | | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+1
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
* | ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
* | mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
* | mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson2016-11-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
* | imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2Eric Nelson2016-11-29-0/+2
| | | | | | | | | | | | | | | | | | Add constants for the MPZQLP2CTL DDR register for both banks to allow setting the LPDDR2 timing values in .cfg files using a named constant instead of hex addresses as is currently done in mx6slevk and other board files. Signed-off-by: Eric Nelson <eric@nelint.com>
* | imx: make ipu's di configurableMax Krummenacher2016-11-29-0/+1
| | | | | | | | | | | | | | | | | | The ipu has two display interfaces. Make the used one a parameter in struct display_info_t instead of using unconditionally DI0. DI0 is the default setting. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Eric Nelson <eric@nelint.com>
* | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2016-11-29-53/+288
|\ \ | |/ | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-11-25-51/+278
| |\ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/Kconfig
| | * armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang2016-11-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-45/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain2016-11-22-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain2016-11-22-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-11-22-0/+4
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| | * | spi: kirkwood_spi: implement mvebu_spi_set_mode()Chris Packham2016-11-18-0/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | Set the appropriate bits in the interface config register based on the SPI_ mode flags. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Chris Packham <judge.packham@gmail.com>
| * | TI: Remove CONFIG_OMAP_COMMON in favor of CONFIG_ARCH_OMAP2Tom Rini2016-11-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | With the move to arch/arm/mach-omap2 there are now very few uses of CONFIG_OMAP_COMMON and further they can all be replaced with CONFIG_ARCH_OMAP2, so do so. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | board: ti: amx3xx: Remove multiple EEPROM readsLokesh Vutla2016-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | | Detect the board very early and avoid reading eeprom multiple times. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | ARM: AMx3xx: Centralize early clock initializationLokesh Vutla2016-11-21-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | This is similar to Commit 93e6253d11030 ("ARM: OMAP4/5: Centralize early clock initialization") that was done for OMAP4+, reflecting the same for AM33xx and AM43xx SoCs to centralize clock initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add setup_early_clocks that calls setup_clocks_for_console for ti81xx] Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-11-17-0/+1
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
| | * ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
| * | ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu2016-11-15-0/+1
| |/ | | | | | | | | | | | | Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | imx: mx6ull: update the REFTOP_VBGADJ settingPeng Fan2016-11-16-0/+1
|/ | | | | | | | | | | | | | | | | | According to design team, we need to set REFTOP_VBGADJ in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the actually table is as below: '000" - set REFTOP_VBGADJ[2:0] to 3'b000 '001" - set REFTOP_VBGADJ[2:0] to 3'b001 '010" - set REFTOP_VBGADJ[2:0] to 3'b010 '011" - set REFTOP_VBGADJ[2:0] to 3'b011 '100" - set REFTOP_VBGADJ[2:0] to 3'b100 '101" - set REFTOP_VBGADJ[2:0] to 3'b101 '110" - set REFTOP_VBGADJ[2:0] to 3'b110 '111" - set REFTOP_VBGADJ[2:0] to 3'b111 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
* arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy2016-11-13-1/+1
| | | | | | | | | | | | | | | | | While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: add hooks for all cache-wide operationsStephen Warren2016-11-07-1/+3
| | | | | | | | | | | | | | SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-01 06:29:57 +0000