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* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-17-2/+63
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| * pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-0/+9
| | | | | | | | | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | | | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | | | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+5
| | | | | | | | | | | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | ARM: make gd a function for clangJeroen Hofstee2014-09-09-0/+25
|/ | | | | | | | | | | | | | | | "clang does not support global register variables; this is unlikely to be implemented soon because it requires additional LLVM backend support" [1] Workaround it by obtaining the value of gd/r9 by an inline asm routine. Note there is no set routine added for ARM at the moment, since most if not all updates of gd from c are actually not needed for ARM. [1] http://clang.llvm.org/docs/UsersManual.html cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-09-15/+29
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| * exynos5420: add callbacks needed for exynos_fb driverAjay Kumar2014-09-05-0/+3
| | | | | | | | | | | | | | | | | | | | Add initialization code for peach_pit panel, parade bridge chip, and backlight. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * ARM: exynos: Add missing declaration for gpio_direction_inputAjay Kumar2014-09-05-0/+1
| | | | | | | | | | | | | | | | This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar2014-09-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos_fb: Remove usage of static definesAjay Kumar2014-09-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arch:exynos: boot mode: add get_boot_mode(), code cleanupPrzemyslaw Marczak2014-09-05-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces code clean-up for exynos boot mode check. It includes: - removal of typedef: boot_mode - move the boot mode enum to arch-exynos/power.h - add bootmode for sequence: eMMC 4.4 ch4 / SD ch2 - add new function: get_boot_mode() for OM[5:1] pin check - update spl boot code Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Changes v5: - exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2) Changes v6: - none changes v7: - change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan2014-09-04-5/+2
|/ | | | | | | | There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
* tegra: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-30-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Tegra board select menu to tegra/Kconfig. Insert the Tegra SoC select menu between the arch select and the board select. Architecture select |-- Tegra Platform (Tegra) |- Tegra SoC select (Tegra20 / 30 / 114 / 124) |- Board select Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows: config TEGRA bool select SPL Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* arm: add Cygnus and NSP boardsScott Branden2014-08-30-0/+67
| | | | | | | | | The bcm_ep board configuration is used by a number of boards including Cygnus and NSP. Add builds for the bcm958300k and the bcm958622hr boards. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* arm: iproc: Initial commit of iproc architecture codeScott Branden2014-08-30-0/+98
| | | | | | | | The iproc architecture code is present in several Broadcom chip architectures, including Cygnus and NSP. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* arm: vf610: add NFC clock supportStefan Agner2014-08-30-0/+15
| | | | | | | Add NFC (NAND Flash Controller) clock support and enable them at board initialization time. Signed-off-by: Stefan Agner <stefan@agner.ch>
* arm: vf610: add NFC pin muxStefan Agner2014-08-30-0/+38
| | | | | | | | Add pin mux for NAND Flash Controller (NFC). NAND can be connected using 8 or 16 data lines, this patch adds pin mux entries for all 16 data lines. Signed-off-by: Stefan Agner <stefan@agner.ch>
* arm: bcm281xx: Add Ethernet Clock supportJiandong Zheng2014-08-30-0/+3
| | | | | | | | Enable Ethernet clock when Broadcom StarFighter2 Ethernet block (CONFIG_BCM_SF2_ETH) is enabled. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* socfpga: initialize designware ethernetPavel Machek2014-08-30-0/+2
| | | | | | | | Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment. Signed-off-by: Pavel Machek <pavel@denx.de>
* socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See2014-08-29-0/+2
| | | | | | | | | | | | | To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: fix clock manager register definitionPavel Machek2014-08-29-43/+49
| | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
* ARM:asm:io.h use static inlineJeroen Hofstee2014-08-29-6/+6
| | | | | | | | | | | When compiling u-boot with W=1 the extern inline void for read* is likely causing the most noise. gcc / clang will warn there is never a actual declaration for these functions. Instead of declaring these extern make them static inline so it is actually declared. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-08-29-6/+44
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| * keystone2: use EFUSE_BOOTROM information to configure PLLsVitaly Andrianov2014-08-25-0/+38
| | | | | | | | | | | | | | | | | | This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * board/ti/dra7xx: add support for parallel NORpekon gupta2014-08-25-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-08-29-19/+3
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| * | ARM: zynq: Remove spl.hMichal Simek2014-08-19-17/+1
| | | | | | | | | | | | | | | | | | | | | | | | Do not specify own zynq specific SPL macros because there is no need for that. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: zynq: Move ps7_init() out of spl.hMichal Simek2014-08-19-2/+2
| | | | | | | | | | | | | | | | | | | | | Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2014-08-29-0/+71
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| * | | ARM: tegra: add Colibri T30 board supportStefan Agner2014-08-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds board support for the Toradex Colibri T30 module. Working functions: - SD card boot - eMMC environment and boot - USB host/USB client (on the dual role port) - Network (via ASIX USB) Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: Disable VPRBryan Wu2014-08-18-0/+58
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-08-29-21/+2069
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| * | | mx6sxsabresd: Add Ethernet supportFabio Estevam2014-08-20-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031. Add support for one FEC port initially. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | ARM: mx5: Fix CHSCCDR nameMarek Vasut2014-08-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the name of the CCM CHSCCDR register. Signed-off-by: Marek Vasut <marex@denx.de>
| * | | mx6: add support of multi-processor commandGabriel Huau2014-08-20-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-11-15/+35
| |\ \ \ | | |/ / | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | | mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADEDFabio Estevam2014-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of register CCM_CIMR corresponds to bit 19 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definitionFabio Estevam2014-08-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Reference Manual the 'wb_per_at_lpm' field of register CCM_CLPCR corresponds to bit 16 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offsetFabio Estevam2014-08-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Reference Manual the 'spdif0_clk_podf' field of register CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset definitions accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6: imx-regs: Remove unused 'omux' field from iomux structFabio Estevam2014-08-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'omux' field is not used anywhere and such layout is not valid for mx6solox. Instead of adding more ifdef's into the structure, let's simply remove this unused 'omux' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-08-214/+673
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| * | | | i.MX6: add enable_spi_clk()Heiko Schocher2014-07-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add enable_spi_clk(), so board code can enable spi clocks. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | | i.MX6: define struct pwm_regs and PWMCR_* definesHeiko Schocher2014-07-23-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add defines for pwm modul found on imx6. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * | | | imx6: add gpr2 usb_otg_id iomux select control defineHeiko Schocher2014-07-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK define for the USB_OTG_ID_SEL bit. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | mx6: Adjust the GPR offset for mx6soloxFabio Estevam2014-07-23-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6solox there is an additional 0x4000 offset for the GPR registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | mx6: Remove duplication of iomuxc structureFabio Estevam2014-07-23-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to keep iomuxc_base_regs structure as it serves the exact same purpose of the iomuxc structure, which is to provide access to the GPR registers. The additional fields of iomuxc_base_regs are not used. Other advantage of 'iomuxc' is that it has a shorter name and the variable declarations can fit into a single line. So remove iomuxc_base_regs structure and use iomuxc instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2014-07-16-241/+689
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> Conflicts: boards.cfg
| * | | | | mx6sx: Add pin definitionsFabio Estevam2014-07-10-0/+1677
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pin definitions for mx6sx. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2025-01-02 18:22:51 +0000