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* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-3287/+2164
|\ | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-0/+4
| | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macroOtavio Salvador2014-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio Estevam <fabio.estevam@freescale.com> and Eric Bénard <eric@eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| * mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+24
| | | | | | | | | | | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-2/+0
| | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-0/+16
| | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2106/+2118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarationsEric Nelson2013-11-13-490/+490
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove unused pad declarationsEric Nelson2013-11-13-1043/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/SoloEric Nelson2013-11-13-0/+24
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: remove useless mux/pad declarationsEric Nelson2013-11-13-160/+0
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-1761/+1761
| | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-0/+45
| | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | | | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+2
| | | | | | | | | | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | | | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+1
| | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | | | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-12/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * \ Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-5/+16
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| | * | am335x: fix GPMC config for NAND and NOR SPL bootpekon gupta2013-11-21-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
| | * | mtd: nand: omap: enable BCH ECC scheme using ELM for generic platformpekon gupta2013-11-21-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta <pekon@ti.com> [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood <scottwood@freescale.com>
| | * | mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
| * | | i2c, omap24xx: convert driver to new mutlibus/mutliadapter frameworkHeiko Schocher2013-11-13-3/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Tom Rini <trini@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Thomas Weber <weber@corscience.de> Cc: Tom Rix <Tom.Rix@windriver.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Luca Ceresoli <luca.ceresoli@comelit.it> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Nishanth Menon <nm@ti.com> Cc: Pali Rohár <pali.rohar@gmail.com> Cc: Peter Barada <peter.barada@logicpd.com> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Michael Jones <michael.jones@matrix-vision.de> Cc: Raphael Assenat <raph@8d.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Stefano Babic <sbabic@denx.de>
| * | omap3_dss: define DSS_ONOFFNikita Kiryanov2013-11-12-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSS_ONOFF to polarity defines Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | ARM: bcm2835: add missing mbox overscan response fieldAndre Heider2013-11-12-0/+1
| |/ | | | | | | | | | | | | | | Add the missing "right" field to struct bcm2835_mbox_tag_overscan. Signed-off-by: Andre Heider <a.heider@gmail.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | at91: redefine legacy GPIO PIN_BASEAndreas Bießmann2013-12-09-1/+1
| | | | | | | | | | | | | | In order to get the very same value for legacy pin definitions and new gpio definitions set the legacy PIN_BASE to 0. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | at91: add new gpio pin definitionsAndreas Bießmann2013-12-09-1/+23
| | | | | | | | | | | | | | | | This patch define new names for GPIO pins on at91 devices. Follow up patches will convert the whole infrastructure to use these new definitions. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-7/+4
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| * | arm: exynos: remove the unused define.Jaehoon Chung2013-12-05-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | These defines didn't use anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos/goni: fix the return type for s5p_mmc_initJaehoon Chung2013-12-05-2/+2
| | | | | | | | | | | | | | | | | | | | | The "int" type is right. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos: spl: Add a custom spi copy functionRajeshwari Shinde2013-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: fix the align for exynos4_power structureMinkyu Kang2013-12-03-1/+1
| |/ | | | | | | | | | | | | res3 should be 4bytes Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dominik Klein <dominik.klein@gmx.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-06-30/+96
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| * | arm: omap3: Enable clocks for peripherals only if they are usedMichael Trimarchi2013-12-06-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * | pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel2013-12-04-0/+4
| | | | | | | | | | | | Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
| * | davinci: fix Master Priority Registers locationViktar Palstsiuk2013-12-04-1/+2
| | | | | | | | | | | | | | | | | | | | | MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@promwad.com>
| * | arm: omap3: Add uart4 omap3 adddressMichael Trimarchi2013-12-04-0/+1
| | | | | | | | | | | | | | | | | | This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
| * | ARM: OMAP5: Add SATA platform glueRoger Quadros2013-12-04-0/+48
| | | | | | | | | | | | | | | | | | Add platform glue logic for the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros2013-12-04-0/+8
| | | | | | | | | | | | | | | | | | | | | Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * | ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039SRICHARAN R2013-12-04-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When core power domain hits oswr, then DDR3 memories does not come back while resuming. This is because when EMIF registers are lost, then the controller takes care of copying the values from the shadow registers. If the shadow registers are not updated with the right values, then this results in incorrect settings while resuming. So updating the shadow registers with the corresponding status registers here during the boot. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: DRA: EMIF: Change DDR3 settings to use hw levelingSRICHARAN R2013-12-04-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | ARM: DRA7: Add is_dra7xx cpu check definitionSRICHARAN R2013-12-04-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | A generic is_dra7xx cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | am33xx: Stop modifying certain EMIF4D registersTom Rini2013-12-04-25/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Javier Martinez Canillas <javier@dowhile0.org> Cc: Heiko Schocher <hs@denx.de> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Matt Porter <matt.porter@linaro.org>
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