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* tegra: i2c: Add I2C driverYen Lin2012-03-29-0/+157
| | | | | | | | | | | | | Add basic i2c driver for Tegra2 with 8- and 16-bit address support. The driver requires CONFIG_OF_CONTROL to obtain its configuration from the device tree. (Simon Glass: sjg@chromium.org modified for upstream) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Enhance clock support to handle 16-bit clock divisorsSimon Glass2012-03-29-2/+8
| | | | | | | | I2C ports have a 16-bit clock divisor. Add code to handle this special case so that I2C speeds below 150KHz are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASESimon Glass2012-03-29-2/+2
| | | | | | | | | Change this name to fit with the current convention in the Tegra header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: Add support for Tegra USB peripheralSimon Glass2012-03-29-0/+254
| | | | | | | | | | | | | | | | | | This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up. Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment: aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; }; drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add function to return peripheral/clock IDSimon Glass2012-03-29-0/+13
| | | | | | | | | A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* EXYNOS: Add structure for Exynos4 DMCChander Kashyap2012-03-27-0/+109
| | | | | | | Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC). Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: Add Prep subcommand support to bootmSimon Schwarz2012-03-27-0/+26
| | | | | | | | | | | | | Adds prep subcommand to bootm implementation of ARM. When bootm is called with the subcommand prep the function stops right after ATAGS creation and before announce_and_cleanup. This is used in command "cmd_spl export" Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* omap-common/spl: Add linux boot to SPLSimon Schwarz2012-03-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This adds Linux booting to the SPL This depends on CONFIG_MACH_TYPE patch by Igor Grinberg (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809) Related CONFIGs: CONFIG_SPL_OS_BOOT Activates/Deactivates the OS booting feature CONFIG_SPL_OS_BOOT_KEY defines the IO-pin number u-boot switch - if pressed u-boot is booted CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normaly RAM-begin + 0x100 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* devkit8000/spl: init GPMC for dm9000 in SPLSimon Schwarz2012-03-27-0/+1
| | | | | | | | | Linux crashes if the GPMC isn't configured for the dm9000. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* mx6: Read silicon revision from registerFabio Estevam2012-03-27-0/+142
| | | | | | | | | | | | | | | Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* mx6: Remove duplicate definition of ANATOP_BASE_ADDRFabio Estevam2012-03-27-1/+0
| | | | | | Remove duplicate definition of ANATOP_BASE_ADDR. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* IXP: Fix GPIO_INT_ACT_LOW_SET()Marek Vasut2012-03-26-2/+8
| | | | | | | | | The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7. This is due to the fact that there are two registers for total of 16 lines. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
* SPL: Add YMODEM over UART load supportMatt Porter2012-03-26-0/+3
| | | | | | | | | | Adds support for loading U-Boot from UART using YMODEM protocol. If YMODEM support is enabled in SPL and the romcode indicates that SPL loaded via UART then SPL will wait for start of a YMODEM transfer via the console port. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registersRobert Delien2012-03-26-31/+13
| | | | | | | | | This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* Introducing 8-bit wide register, mx28_register_8Robert Delien2012-03-26-0/+16
| | | | | | | | | | This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8Robert Delien2012-03-26-417/+421
| | | | | | | | | This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* usb/ehci: Add USB support for the MX6QWolfgang Grandegger2012-03-26-0/+4
| | | | | | | Currently, only USB Host 1 is supported. Cc: Remy Bohmer <linux@bohmer.net> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* i.mx28: Added register definitions for DIGCTL registersRobert Delien2012-03-26-0/+156
| | | | | | | This patch adds register definitions for the registers of the DIGCTL IP-block. Signed-off-by: Robert Delien <robert@delien.nl>
* USB: Armada100: EHCI Driver for Armada100 SOCsAjay Bhargav2012-03-19-0/+1
| | | | | | This patch adds support for USB EHCI driver for Armada100 SOCs. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* USB: Armada100: Add UTMI PHY interface driverAjay Bhargav2012-03-19-0/+87
| | | | | | | This patch adds USB host controller's UTMI PHY interface driver for Armada100 SOCs. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* tt01: add video supportHelmut Raiger2012-02-27-0/+1
| | | | | | | | The video setup for the Epson display is provided. Addtionally some extra info is displayed next to the Linux logo. Make get_cpu_rev() publicly available (added to sys_proto.h). Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* net: fec_mxc: add 1000 Mbps selectionTroy Kisky2012-02-27-0/+1
| | | | | | | | Define FEC_QUIRK_ENET_MAC and add to arch-mx6/imx-regs.h Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* am33xx: ddr_defs.h: Change DDR timingsChase Maupin2012-02-27-1/+1
| | | | | | | | * For cold silicon the DDR timings need to be relaxed in order for the device to boot with DDR at 266MHz * Fix proposed by James Doublesin Signed-off-by: Chase Maupin <Chase.Maupin@ti.com>
* mx6q: Add support for ECSPI through mxc_spi driverEric Nelson2012-02-27-0/+44
| | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* mxc_spi: move machine specifics into CPU headersEric Nelson2012-02-27-0/+82
| | | | | | | | | | | | | | Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU Introduce two new macros to control conditional setup MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x) Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org> Tested-by: Jason Liu <jason.hui@linaro.org>
* mx6q: define GPIO macros for translating between ordinals and port:indexEric Nelson2012-02-27-0/+4
| | | | | | | | | | | | | | | | | The interface to the mxc_gpio driver uses integer (ordinal) values to refer to all GPIOs on the i.MX processors. The registers themselves and much of the i.MX documentation are banked in groups of 32, and these macros allow the use of the port:index numbering for clarity. GPIO_NUMBER() converts to ordinal value from port:index GPIO_PORT() returns the port of an ordinal value GPIO_INDEX() returns the index or offset of the ordinal. Discussion on the mailing list at http://lists.denx.de/pipermail/u-boot/2012-January/116927.html Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* omap_hsmmc: Wait for CMDI to be clearTom Rini2012-02-15-4/+4
| | | | | | | | | | | | | | | | | Before we can send a command we need both the DATI (command inhibit on mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear. The previous behavior of only checking on DATI was insufficient on some cards and incorrect behavior in any case. This makes the code check for both bits being clear and makes the error print more clear as to what happened. DATI_CMDDIS is removed as it was unused elsewhere in the code and stood for 'DATI is set, cmds are disabled still'. Fix originally spotted by Peter Bigot. Tested-by: Peter A. Bigot <bigotp@acm.org> Tested-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
* Changes to move hawkboard to the new spl infrastructureSughosh Ganu2012-02-12-0/+9
| | | | | | | | | | | | | | | | | | This patch moves hawkboard to the new spl infrastructure from the older nand_spl one. Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* ARMV7: Fix duplicate use of "b" parameter in ACTIM_CTRLA definitionPeter Barada2012-02-12-28/+29
| | | | | | | | ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS() instead of "c". To make usage more clear, replace all single-letter macro parameters with more descriptive parameter names. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
* davinci: add support for printing clock frequencyHadli, Manjunath2012-02-12-0/+3
| | | | | | | | | add support for printing various clock frequency info found in SOC such as ARM core frequency, DSP core frequency and DDR frequency as part of bdinfo command. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
* AM3517: Changed default clock rate for AM3517Schuyler Patton2012-02-12-1/+1
| | | | | | | | | | | | AM3517: Changed default clock rate for AM3517 Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows the AM3517 to boot up at 600MHz instead of 500 MHz Signed-off-by: Schuyler Patton <spatton@ti.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@gmail.com> CC: Stefano Babic <sbabic@denx.de>
* OMAP3+: Clock: Adding ehci clock enablingGovindraj.R2012-02-12-0/+1
| | | | | | | | | | Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* ehci-omap: Clean up added ehci-omap.cGovindraj.R2012-02-12-24/+212
| | | | | | | | | | | | | | | | | | Clean up added ehci-omap.c and make it generic for re-use across omap-soc having same ehci ip block. Also pass the modes to be configured from board file and configure the ports accordingly. All usb layers are not cache aligned, till then keep cache off for usb ops as ehci will use internally dma for all usb ops. * Add a generic common header ehci-omap.h having common ip block data and reg shifts. * Rename and modify ehci-omap3 to ehci.h retain only conflicting sysc reg shifts remove others and move to common header file. * pass the board data for beagle/panda accordinly to use ehci ports. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
* ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap2012-02-12-7/+651
| | | | | | | | Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* S5P: support generic watchdog timerMinkyu Kang2012-02-12-1/+64
| | | | | | | | This patch adds support the generic watchdog timer for s5pc1xx and exynos4 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: HeungJun, Kim <riverful.kim@samsung.com>
* ARMV7: Exynos4: Add supoort power for Exynos4HeungJun, Kim2012-02-12-0/+231
| | | | | | | | This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power. Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARMV7: Exynos4: Add watchdog.h for Exynos4HeungJun, Kim2012-02-12-0/+53
| | | | | | | | This patch add watchdog.h for Exynos4 Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: PWM: Add TCMPB3 field in pwm structureChander Kashyap2012-02-12-1/+1
| | | | | | | Add TCMPB3 field in pwm structure, earliar this was res1. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* orion5x: add USB host ehci-marvell supportAlbert ARIBAUD2012-02-12-0/+12
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Remove kirkwood-specifics from marvell EHCI driverAlbert ARIBAUD2012-02-12-0/+12
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Rename ehci-kirkwood as ehci-marvellAlbert ARIBAUD2012-02-12-1/+1
| | | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
* mmc: access mxcmmc from mx31 boardsHelmut Raiger2012-02-12-15/+23
| | | | | | | | | | | | | | | | | This patch modifies mxcmmc.c to be used not only by i.MX27 but also by i.MX31 boards. Both use the same SD controller, but have different clock set-ups. The i.MX27 imx_get_XXXclock functions are made static to generic.c and a public mxc_get_clock() function is provided. Pins, base address and prototypes for an i.MX31 specific board_init_mmc() are provided. Some of the i.MX27 clock getters are unused and marked as such to avoid warnings (./MAKEALL -s mx27), but the code was left in for future use. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx6: mx6x_pins: Fix uart txd definitionsTroy Kisky2012-02-12-24/+12
| | | | | | | | | | | | | The uart txd pad can also provide the rxd function. But it does not stop its tx role. This could be used for a half duplex serial port. Change names to reduce confusion. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* arm, davinci: add timer defines for tcr fieldHeiko Schocher2012-02-12-0/+13
| | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com>
* arm, davinci: add workaround for not resetting DMA bus and VPSS modulesHeiko Schocher2012-02-12-1/+12
| | | | | | | | | | The Buffer Logic of VPSS is Not Reset by System Reset Pin, see http://www.ti.com/lit/er/sprz316b/sprz316b.pdf chapter Advisory 1.2.1 on page 9. Add workaroundcode proposed in the errata. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com>
* arm, davinci: add PLL0 prediv to da850 lowlevel setupBen Gardiner2012-02-12-1/+2
| | | | | | | | | | | | | | | | The OMAP-L138 has a pre-divider available on PLL0. Add support to da850_lowlevel.c for configuring PLL0's pre-divider. This is to achieve certain OPP's -- e.g. the 372MHz OPP used also by Linux. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Cc: Christian Riesch <christian.riesch@omicron.at> CC: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Tom Rini <tom.rini@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* tegra: Add SDMMC support to funcmuxSimon Glass2012-02-12-0/+8
| | | | | | | | | This adds support for SDMMC ports to the funcmux. Only one option is supported: FUNCMUXO_SDMMC_8BIT which selects an 8-bit wide SDIO interface where available. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add I2C support to funcmuxSimon Glass2012-02-12-0/+7
| | | | | | | | Add support to funcmux for selecting I2C functions and programming the pinmux appropriately. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add enum to select from available funcmux configsSimon Glass2012-02-12-1/+11
| | | | | | | | | We want to give a name to each available funcmux config. For now we just use the pin group names (even through it is verbose) since there seems to be nothing better. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Adjust funcmux config test to permit expansionSimon Glass2012-02-12-0/+3
| | | | | | | | We want to support config options other than zero, so move the test to the end to allow intermediate code to OK such a config. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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