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| * | | am335x_evm: Add support for the NOR module on the memory capeSteve Kipisz2013-07-30-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com>
| * | | ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-07-26-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-07-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-07-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-5229/+370
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| * | | ARM: highbank: set timer prescaler to 256Rob Herring2013-07-25-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-videoTom Rini2013-08-12-114/+4
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| * | | exynos: video: change mipi dsi write function parameters correctlyDonghwa Lee2013-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch have changed mipi dsi write functions' parameters correctly so that type cast operations were removed. And mipi dsi payload is composed with array of panel commands to improve readability. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
| * | | arm, am33xx: add clk_get prototypeHeiko Schocher2013-08-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the clk_get() function is needed for the da8xx-fb video driver, which is used on the am3xx based siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | video, da8xx: move da8xx-fb.h to drivers/videoHeiko Schocher2013-08-10-113/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the da8xx-fb driver works also on am335x boards. So move the da8xx-fb.h file from arch/arm/include/asm/arch-davinci to drivers/video, so this driver can used from am335x based boards. Also add WVGA panel_type. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | dma: apbh: Add special circular mode for LCDMarek Vasut2013-08-09-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add special function that executes a specially crafted circular DMA descriptor. The function doesn't wait for the descriptor to finish the transfer, since the descritor never finishes. This is useful when operating a SmartLCD through the LCDIF interface, as the LCDIF does not give us any means to have continuous refresh of the SmartLCD. Instead, the RUN bit in the LCDIF CTRL register must be triggered manually. This can be worked around by starting an DMA transfer which continuously sets the RUN bit. This function allows starting exactly such transfer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | | spi: Add zynq spi controller driverJagannadha Sutradharudu Teki2013-08-07-0/+2
|/ / | | | | | | | | | | | | | | | | Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-24-1/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * | vf610: Add I2C support for Vybrid VF610 platformAlison Wang2013-07-23-0/+7
| | | | | | | | | | | | | | | | | | | | | This patch adds I2C support for Vybrid VF610 platform and adds I2C0 support to VF610TWR board. Signed-off-by: Alison Wang <b18965@freescale.com>
| * | i2c, soft-i2c: switch to new multibus/multiadapter supportHeiko Schocher2013-07-23-1/+1
| |/ | | | | | | | | | | | | | | | | - added to soft_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-5228/+362
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-07-12-169/+2133
|\ | | | | | | | | | | | | | | | | | | Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114Jim Lin2013-07-11-139/+532
| | | | | | | | | | | | | | | | | | | | Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-07-10-6/+20
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| | * EXYNOS: Move files from board/samsung to arch/armRajeshwari Shinde2013-07-05-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch performs the following: 1) Convert the assembly code for memory and clock initialization to C code. 2) Move the memory and clock init codes from board/samsung to arch/arm 3) Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code 4) Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5. 5) Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main. 6) exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250. TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS: Add API for power reset and exit wakeupRajeshwari Shinde2013-07-05-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds APIs to get power reset status and exit the wakeup condition for both exynos5 and exynos4 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * SMDK5250: Remove reduntant codeRajeshwari Shinde2013-06-28-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enum boot_mode is defined twice once in spl.h and also in spl_boot.c, hence removing the same from spl_boot.c and including the header file. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5Axel Lin2013-07-02-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs. These SoCs have different gpio count but currently omap_gpio driver uses hard coded 192 which is wrong. This patch fixes this issue by: 1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h. 2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5. Thanks for Lubomir Popov to provide valuable comments to fix this issue. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Lubomir Popov <lpopov@mm-sol.com> Acked-by: Heiko Schocher <hs@denx.de>
| * | am33xx: fix the ddr_cmdtctrl structureIlya Ledvich2013-07-02-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the wrong mapping between the DDR I/O control registers on AM33XX SoCs and the software representation in the SPL code. The most recent public TRM defines the following DDR I/O control registers offsets: * ddr_cmd0_ioctrl : offset 0x44E11404 * ddr_cmd1_ioctrl : offset 0x44E11408 * ddr_cmd2_ioctrl : offset 0x44E1140C * ddr_data0_ioctrl: offset 0x44E11440 * ddr_data1_ioctrl: offset 0x44E11444 While the struct ddr_cmdtctrl has also some reserved bits in the beginning. The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because of this mapping mismatch. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-28-23/+1571
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| | * mx27: add i2c clocktrem2013-06-26-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
| | * imx: Complete the pin definitions for the i.MX6DL / i.MX6SoloPierre Aubert2013-06-26-22/+1569
| | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
| | * imx6: fix GPR2 wrong definitionPierre Aubert2013-06-26-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Dirk Behme <dirk.behme@gmail.com>
* | | exynos: Avoid function instrumentation for microsecond timerSimon Glass2013-06-26-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For tracing to work it has to be able to access the microsecond timer without causing a recursive call to the function entry/exit handlers. Add attributes to the relevant functions to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-22-40/+57
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| * | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-19-0/+4
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| | * | arm, am33xx: move uart soft reset code to common placeHeiko Schocher2013-06-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | move uart soft reset code to common place and call this function from board code, instead of copy and paste this code for every board. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Tom Rini <trini@ti.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Acked-by: Tom Rini <trini@ti.com> [trini: Fix igep0033 build, remove 'regval' on pcm051] Signed-off-by: Tom Rini <trini@ti.com>
| | * | arm, am335x: make mpu pll config configurableHeiko Schocher2013-06-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | upcoming support for siemens boards switches mpu pll clk in board code. So make this configurable. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
| | * | arm, am33xx: move rtc32k_enable() to common placeHeiko Schocher2013-06-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | move rtc32k_enable() to common place so all am33xx boards can use it. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Matt Porter <mporter@ti.com> Cc: Lars Poeschel <poeschel@lemonage.de> Cc: Tom Rini <trini@ti.com> Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
| * | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-19-40/+53
| |\ \ \ | | |/ / | |/| | | | | | | | | | Conflicts: spl/Makefile
| | * | power: exynos-tmu: fix warnings and clean up codeNaveen Krishna Chatradhi2013-06-13-33/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the folowing 1. change the data types for unsigned int variable to unsigned 2. change the tmu_base type to struct exynos5_tmu_reg * 3. Add timer functionality for get_cur_temp() 4. error handling in the get_tmu_fdt_values() 5. Add check for curr_temp reading 6. some cosmotic changes. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | EXYNOS5: DWMMC: Added FDT support for DWMMCAmar2013-06-13-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: update tzpc to make it common for exynos4 and exynos5Inderpal Singh2013-06-04-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: move tzpc_init to armv7/exynosInderpal Singh2013-06-04-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tzpc_init is common for all exynos5 boards, hence move it to armv7/exynos so that all other boards can use it. Also update the smdk5250 Makefile and config file. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-13-1073/+1011
|\ \ \ \ | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR Conflicts: arch/arm/include/asm/arch-omap5/omap.h Signed-off-by: Tom Rini <trini@ti.com>
| * | | arm: da830: moved pinmux configurations to the arch treeVishwanathrao Badarkhe, Manish2013-06-10-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move pinmux configurations for the DA830 SoCs from board file to the arch tree so that it can be used for all da830 based devices. Also, avoids duplicate pinmuxing in case of NAND. Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
| * | | OMAP5: Enable access to auxclk registersLubomir Popov2013-06-10-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * | | arm: Remove OMAP2420H4 and all omap24xx supportTom Rini2013-06-10-932/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap2420H4 was the only mainline omap24xx board. Prior to being fixed by Jon Hunter in time for v2013.04 it had been functionally broken for a very long time. Remove this board as there's not been interest in it in U-Boot for quite a long time. Signed-off-by: Tom Rini <trini@ti.com>
| * | | ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-06-10-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-06-10-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * | | ARM: DRA7xx: Update pinmux dataLokesh Vutla2013-06-10-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
| * | | mmc: omap_hsmmc: Update pbias programmingBalaji T K2013-06-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Correct SRAM END addressSricharan R2013-06-10-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Correct the SYS_CLK to 20MHZSricharan R2013-06-10-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-06-10-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-11-01 13:36:57 +0000