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* | video: support exynos display port driversDonghwa Lee2012-09-01-0/+965
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch set supports exynos display port drivers. DisplayPort is an industry standard device to accommodate the increasing board adoption of digital display technology within the PC and consumer electronics. The interface supports internal chip-to-chip and external box-to-box digital display connections. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: add display port base addressDonghwa Lee2012-09-01-0/+3
| | | | | | | | | | | | | | | | | | This patch add display port base address for EXYNOS5. In case of EXYNOS4, use DEVICE_NOT_AVAILABLE macro because DP is not supported. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: support display port phy control functionDonghwa Lee2012-09-01-0/+5
| | | | | | | | | | | | | | | | This patch support display port phy control function. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | video: support exynos fimd driver for various exynos seriesDonghwa Lee2012-09-01-1/+24
| | | | | | | | | | | | | | | | | | This patch supports exynos fimd driver for various exynos series different from existing it supports only exynos4 chip. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-2/+5
| | | | | | | | | | | | | | | | | | | | This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde2012-09-01-0/+3
| | | | | | | | | | | | | | | | This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-0/+65
| | | | | | | | | | | | | | | | The patch adds the memory initialization sequence of DDR3. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-108/+126
| | | | | | | | | | | | | | | | | | Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARCH: SPL: Add parametric board initializerRajeshwari Shinde2012-09-01-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a structure for table-driven configuration mechanism such that no recompilation is needed to update the configuration parameters, rather than hard-coding board initialization parameters. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | ARM: add tegra20 support to arm720tAllen Martin2012-09-01-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-26/+26
| | | | | | | | | | | | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: add basic support for the Broadcom BCM2835 SoCStephen Warren2012-09-01-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This SoC is used in the Raspberry Pi, for example. For more details, see: http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Initial support is enough to boot to a serial console, execute a minimal set of U-Boot commands, download data over a serial port, and boot a Linux kernel. No storage or network drivers are implemented. GPIO driver originally by Vikram Narayanan <vikram186@gmail.com> with many fixes from myself. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | u8500: Enabling power to MMC device on AB8500 V2Mathieu J. Poirier2012-09-01-2/+20
| | | | | | | | | | | | | | | | | | Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* | u8500: Moving processor-specific functions to cpu area.Mathieu J. Poirier2012-09-01-0/+1
| | | | | | | | | | | | | | | | | | | | Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* | snowball: applying power to LAN and GBF controllersMathieu J. Poirier2012-09-01-3/+15
| | | | | | | | | | | | | | | | LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* | snowball: Moving to ux500.v2 addess scheme for PRCMU accessMathieu J. Poirier2012-09-01-4/+8
| | | | | | | | | | | | | | | | Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* | snowball: Adding CPU clock initialisationMathieu J. Poirier2012-09-01-4/+1
| | | | | | | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* | snowball: Adding architecture dependent initialisationMathieu J. Poirier2012-09-01-5/+19
| | | | | | | | | | | | | | Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* | u8500: Moving prcmu to cpu directoryMathieu J. Poirier2012-09-01-0/+55
| | | | | | | | | | | | | | | | This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* | snowball: Add support for ux500 based snowball boardMathieu J. Poirier2012-09-01-0/+212
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Acked-by: Tom Rini <trini@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/gpio/Makefile
* | am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya2012-09-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
* | da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu2012-09-01-0/+106
| | | | | | | | | | | | | | | | | | | | Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* | omap4/5/am33xx: Make lowlevel_init available to all armv7 platformsTom Rini2012-09-01-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Correct MMC1, remove MMC2 supportTom Rini2012-09-01-3/+2
| | | | | | | | | | | | | | | | - Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
* | mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador2012-09-01-2/+2
| | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-16/+16
| | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mxs: prefix register acessor macros with 'mxs' prefixOtavio Salvador2012-09-01-509/+509
| | | | | | | | | | | | | | As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | mxs: reorganize source directory for easy sharing of code in i.MXS SoCsOtavio Salvador2012-09-01-0/+0
| | | | | | | | | | | | | | | | | | Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* | MX28: extend print_cpuinfo() to use chip informationOtavio Salvador2012-09-01-0/+4
| | | | | | | | | | | | | | The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | arm : Atmel : add at91sam9x5ek board supportBo Shen2012-09-01-0/+265
| | | | | | | | | | | | | | | | | | | | | | | | Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: Bo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | DaVinci DA8xx: replace magic number for DDR speedLaurence Withers2012-09-01-0/+2
| | | | | | | | | | | | | | | | | | | | Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* | DaVinci DA850: UART2 clock ID comes from ASYNC3Laurence Withers2012-09-01-1/+3
| | | | | | | | | | | | | | | | | | | | On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* | DaVinci DA8xx: tidy up clock ID definitionLaurence Withers2012-09-01-16/+40
| | | | | | | | | | | | | | | | | | | | | | Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Rework pinmux functionsTom Rini2012-09-01-26/+28
| | | | | | | | | | | | | | | | | | | | - Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Add support for TI AM335x StarterKit EVMTom Rini2012-09-01-0/+1
| | | | | | | | | | | | | | | | | | | | - Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-01-0/+17
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Correct and clean up ddr_regs structTom Rini2012-09-01-19/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-01-18/+7
| | | | | | | | | | | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-01-12/+1
| | | | | | | | | | | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-01-34/+4
| | | | | | | | | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-01-6/+6
| | | | | | | | | | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini2012-09-01-0/+1
| | | | | | | | | | | | | | | | | | - Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
* | am335x: ddr_defs: Update EMIF parametersVaibhav Bedia2012-09-01-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini2012-09-01-20/+12
| | | | | | | | | | | | | | - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-01-0/+1
| | | | | | | | | | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Pass to config_ddr the type of memory that is connectedTom Rini2012-09-01-2/+8
| | | | | | | | | | | | | | | | | | We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-01-2/+2
| | | | | | | | | | | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Convert to using <asm/emif.h> to describe the EMIFTom Rini2012-09-01-27/+0
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx: Remove DMM_BASE defineTom Rini2012-09-01-1/+0
| | | | | | | | | | | | The am33xx does not have a DMM, so don't define the base. Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-12 23:11:59 +0000