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* bcm281xx: add support for "USB OTG clock"Steve Rae2014-12-29-0/+3
| | | | | | | | enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
* ARM: rpi: support model A+Stephen Warren2014-12-29-0/+1
| | | | | | | Add a board rev entry for the new model A+, and augment the board rev error handling code to be a bit more verbose. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* arm: semihosting: fix up compile bugsLinus Walleij2014-12-29-1/+1
| | | | | | | | | | | | | | | | | | | | There is currently a regression when using newer ARM64 compilers for semihosting: the way long types are inferred from context is no longer the same. The semihosting runtime uses long and size_t, so use this explicitly in the semihosting code and interface, and voila: the code now works again. Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Suggested-by: Mark Hambleton <mark.hambleton@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* arm: semihosting: staticize internal functionsLinus Walleij2014-12-29-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | The semihosting code exposes internal file handle handling functions to read(), open(), close() and get the length of a certain file handle. However the code using it is only interested in either reading and entire named file into memory or getting the file length of a file referred by name. No file handles are used. Thus make the file handle code internal to this file by removing these functions from the semihosting header file and staticize them. This gives us some freedom to rearrange the semihosting code without affecting the external interface. Cc: Darwin Rambo <drambo@broadcom.com> Cc: AKASHI Takahiro <takahiro.akashi@linaro.org> Cc: Mark Hambleton <mark.hambleton@arm.com> Cc: Tom Rini <trini@ti.com> Acked-by: Steve Rae <srae@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-12-16-1/+2
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| * socfpga: correctly increment freeze_controller_base addressDinh Nguyen2014-12-06-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Correctly increment the base address of the freeze controller. And since SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * socfpga: add missing struct member fifo_triple_byteDinh Nguyen2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | socfpga_scan_manager structure was missing a data member. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Vince Bridgers <vbridger@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de>
| * arm: socfpga: Add missing DW master SPI clock prototyp to clock_manager.hStefan Roese2014-12-06-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* | Merge git://git.denx.de/u-boot-dmTom Rini2014-12-11-1/+1
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| * | dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-0/+5
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-12-11-0/+186
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| * | | ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | ls102xa: changing a few targets' configurations.Xiubo Li2014-12-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR boardAlison Wang2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add SD boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Update PCIe dts node statusMinghuan Lian2014-12-11-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: clear EPU registers for deep sleepchenhui zhao2014-12-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-12-10-4/+12
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| * | | | arm: vf610: improve evaluation of reset sourceStefan Agner2014-12-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the evaluation of the reset source. Bit description according to latest reference manual rev. 7. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | | | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-12-10-0/+215
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| * | | | | arm: rmobile: Add mmc.h for sh_mmcif of rmobileNobuhiro Iwamatsu2014-12-10-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver. This adds arch-rmobile/mmc.h that defines mmcif_mmc_init(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add structure for infomation of module control registerNobuhiro Iwamatsu2014-12-05-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The infomation of module control register for R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are almost the same, they can be combined into one structure. This provides structure that summarizes infomation of module control register and default register values. And this structure is the module control use of the kernel at boot time. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add infomation of bits for module control registerNobuhiro Iwamatsu2014-12-05-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds infomation of bits for module control register. This is used to control modules on ARM R-Car SoCs. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Add mstp_setclrbits and mstp_setclrbits_le32Nobuhiro Iwamatsu2014-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This addes macro for set and clear bit control for module control register. This is used when user want to disable the function of the devices corresponding to register. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Move control macro of mstp to arch-rmobile/rcar-mstp.hNobuhiro Iwamatsu2014-12-05-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Control macro of mstp is common in R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794). This moves these to arch-rmobile/rcar-mstp.h Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | | arm: rmobile: rcar: Move module control register to header file of SoCNobuhiro Iwamatsu2014-12-05-0/+39
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Module control registers of R-Car ARM SoC (r8a7790, r8a7791, r8a7793 and r8a7794) are same address. This moves these to header file of SoC. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | | | stv0991: enable ethernet supportVikas Manocha2014-12-09-0/+72
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | | | stv0991: Add basic stv0991 architecture supportVikas Manocha2014-12-09-0/+365
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | stv0991 architecture support added. It contains the support for following blocks - Timer - uart Signed-off-by: Vikas Manocha <vikas.manocha@st.com> [trini: Add arch/arm/cpu/armv7/Makefile hunk] Signed-off-by: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-12-08-8/+12
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| * | | | arm: am33xx: Handle NAND+I2C boot-device the same way as NANDStefan Roese2014-12-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-map NAND&I2C boot-device to the "normal" NAND boot-device. Otherwise the SPL boot IF can't handle this device correctly. Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens Draco leads to this boot-device passed to SPL from the BootROM. With this change, Draco boots just fine into main U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
| * | | | arm: omap: add support for am57xx devicesFelipe Balbi2014-12-04-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap_common: expose tps659038 and dra7xx_dpllsFelipe Balbi2014-12-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | expose those two definitions so they can be used by another board which we're adding in upcoming patches. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-04-5/+5
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-12-08-0/+7
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| * | | | ARM: UniPhier: detect the number of flash banks at run-timeMasahiro Yamada2014-12-09-0/+7
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some UniPhier boards are equipped with an expansion slot that some optional SRAM/NOR-flash cards can be attached to. So, run-time detection of the number of flash banks would be more user-friendly. Until this commit, UniPhier boards have achieved this by (ab)using board_flash_wp_on() because the boot failed if flash_size got zero. Fortunately, this problem was solved by commit 70879a92561a (flash: do not fail even if flash_size is zero). Now it is possible to throw away such a tricky workaround. This commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further refactoring. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: rpi_b: detect board revisionStephen Warren2014-12-08-0/+33
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect the board revision early during boot, and print the decoded model name. Eventually, this information can be used for tasks such as: - Allowing/preventing USB device mode; some models have a USB device on- board so only host mode makes sense. Others connect the SoC directly to the USB connector, so device-mode might make sense. - The on-board USB hub/Ethernet requires different GPIOs to enable it, although luckily the default appears to be fine so far. - The compute module contains an on-board eMMC device, so we could store the environment there. Other models use an SD card and so don't support saving the environment (unless we store it in a file on the FAT boot partition...) Set $fdtfile based on this information. At present, the mainline Linux kernel doesn't contain a separate DTB for most models, but I hope that will change soon. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-27-0/+6
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| * | | ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROLMasahiro Yamada2014-11-28-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. Consequently, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. In the first place, GPIO has nothing to do with OF_CONTROL. It is wrong that lib/fdtdec.c includes GPIO functions; it should be split into two files, FDT-common things and GPIO things. It is, however, a pretty big work to fix that correctly. This is a compromised commit to add a dummy <asm/arch/gpio.h> to support OF_CONTROL for UniPhier platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | mtd: nand: s3c: Unify the register definition and namingMarek Vasut2014-11-26-20/+19
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Vladimir Zapolskiy <vz@mleia.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-3/+18
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| * | | arm: ls102xa: Remove bit reversing for SCFG registersAlison Wang2014-11-24-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCFG_SCFGREVCR is SCFG bit reverse register. This register must be written with 0xFFFFFFFF before writing to any other SCFG register. Then other SCFG register could be written in big-endian mode. Address: 157_0000h base + 200h offset = 157_0200h Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 W/R SCFGREV Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0-31 SCFGREV SCFG Bit Reverse Control Filed 32'h 0000_0000 - No bit reverse is applied 32'h FFFF_FFFF - Bit reverse is applied; so 31:0 will be stored/read as 0:31 This patch removes the bit reversing for SCFG registers in u-boot. It will be implemented through PBI commands in RCW .pbi write 0x570200, 0xffffffff .end So other SCFG register could be written in big-endian mode in u-boot or kernel directly. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Add snoop disable for slave port 0, 1 and 2Jason Jin2014-11-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable the snoop for slave interface 0, 1 and 2 to avoid the interleaving on the CCI400 BUS. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | drivers: usb: fsl: Define USB configs for LS102XANikhil Badola2014-11-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR, CONFIG_USB_MAX_CONTROLLER_COUNT Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | arm: ls102xa: Fixed a register definition errorTang Yuantian2014-11-19-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 8 SCFG_SPARECR registers in SCFG memory block, not one. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | qe: add u-qe support to arm boardZhao Qiang2014-11-19-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ls1021 is arm-core and support qe which is u-qe. add u-qe init for arm board. Signed-off-by: Zhao Qiang <B45475@freescale.com> [York Sun: Fix compiling error caused by u_qe_init()] Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-05 10:43:30 +0000