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* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-03-4/+6
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| * ARM: mxs: allow boards to select DC-DC switching clock sourceMichael Heimpold2016-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, override the mxs_power_setup_dcdc_clocksource function in your board support files. Example: void mxs_power_setup_dcdc_clocksource(void) { mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ); } Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * imx: mx6: fix reg base address when runtime usagePeng Fan2015-12-07-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Should use parenthese to wrap the macro definition, otherwise we will encounter error like the following: " if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; } " Without this patch, we will always encounter "Wrong LCD interface". Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | armv8/ls1043a: Implement workaround for PEX erratum A009929Mingkai Hu2015-12-17-0/+2
| | | | | | | | | | | | | | | | | | Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/fsl_lsch2: fix DCSR_DCFG addressMingkai Hu2015-12-17-1/+1
| | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-14-12/+84
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| * | armv8: Add sata support on Layerscape ARMv8 boardTang Yuantian2015-12-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-15-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv7/fsl-ls102xa: Workaround for DDR erratum A008514Yao Yuan2015-12-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a workaround for hardware erratum. Write the value of 63b2_0042h to EDDRTQCFG will optimal the memory controller performance. The value: 63b2_0042h comes from the hardware team. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: enable all the snoop signal for masters.Yao Yuan2015-12-13-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the IP feature's snoop signal to support hardware snoop for cache coherence. SNPCNFGCR contains the bits to drive snoop signal for various masters. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-13-0/+12
| | | | | | | | | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102x: add get_svr and IS_SVR_REV helperShengzhou Liu2015-12-13-0/+5
| | | | | | | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | stm32: Convert serial driver to DMKamil Lulko2015-12-12-1/+9
|/ / | | | | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Add support for Allwinner A83T DRAMvishnupatekar2015-12-10-0/+203
| | | | | | | | | | | | | | | | | | | | | | Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: clk: add basic clocks for A83Tvishnupatekar2015-12-10-1/+307
| | | | | | | | | | | | | | | | | | | | | | Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add support for UART0 in PB pin group on A83Tvishnupatekar2015-12-10-0/+1
| | | | | | | | | | | | | | | | | | | | On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Set AHB1 clock to PLL6/3 on all clock_sun6i.h using SoCsHans de Goede2015-12-10-4/+0
| | | | | | | | | | | | | | | | | | | | | | According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Chen-Yu Tsai <wens@csie.org>
* | zynq: sdhci: Move driver to DMMichal Simek2015-12-07-4/+0
| | | | | | | | | | | | | | Move driver to DM Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: zynq: Remove unused SERIAL macros for serial_zynqMichal Simek2015-12-07-3/+0
| | | | | | | | | | | | Remove unused macros when driver was moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Change e-mail address of Kamil LulkoKamil Lulko2015-12-05-5/+5
| | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-04-1/+1
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| * iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-25-1/+1
| | | | | | | | | | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+341
| | | | | | | | | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add early uart driverhuang lin2015-12-01-0/+44
| | | | | | | | | | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | | | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+168
| | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add timer driverhuang lin2015-12-01-0/+22
| | | | | | | | | | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-30-41/+116
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| * | armv8: fsl-layerscape: Fix early MMU table for nand bootYork Sun2015-11-30-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early MMU table doesn't enable all addresses. Unused addresses are marked as invalid, as introduced by commit 9979922. An entry was missing for NAND flash space, causing nand boot failure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
| * | armv8: ls2085a: Add workaround of errata A009635Prabhakar Kushwaha2015-11-30-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the core runs at higher than x3 speed of the platform, there is possiblity about sev instruction to getting missed by other cores. This is because of SoC Run Control block may not able to sample the EVENTI(Sev) signals. Configure Run Control and EPU to periodically send out EVENTI signals to wake up A57 cores. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/layerscape: Update MMU table with execute-never bitsAlison Wang2015-11-30-28/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
| * | drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3York Sun2015-11-30-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Freescale LSCH3 platforms use two DDR controlers interleaving mode out of reset. It can be configured to disable one controller. To support this operation, the driver needs to detect and skip the disabled controller. Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043ardb: add USB supportGong Qianyu2015-11-30-3/+3
| | | | | | | | | | | | | | | | | | | | | Add support for the third USB controller for LS1043A. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | pci/layerscape: add support for LS1043A PCIe LUT register accessMingkai Hu2015-11-30-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The endian and base address of PEX LUT register region is different between Chassis 2 and Chassis 3, so move the base address definition to chassis specific header file and add pex_lut_* functions to access LUT register. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: ls2085a: Add support of LS2085A SoCPrabhakar Kushwaha2015-11-30-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's LS2085A is a another personality of LS2080A SoC with support of AIOP and DP-DDR. This Patch adds support of LS2085A Personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Updated MAINTAINERS files Dropped #ifdef in cpu.h Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-30-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bitAlison Wang2015-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addresses a problem mentioned recently on this mailing list: [1]. In that posting a LS1021 based system was locking up at about 5 minutes after boot, but the problem was mysteriously related to the toolchain used for building u-boot. Debugging the problem reveals a stuck interrupt 29 on the GIC. It appears Freescale's LS1021 support in u-boot erroneously sets the 64-bit ARM generic PL1 physical time CompareValue register to all-ones with a 32-bit value. This causes the timer compare to fire 344 seconds after u-boot configures it. Depending on how fast u-boot gets the kernel booted, this amounts to about 5-minutes of Linux uptime before locking up. Apparently the bug is masked by some toolchains. Perhaps this is explained by default compiler options, word sizes, or binutils versions. At any rate this patch makes the manipulation explicitly 64-bit which alleviates the issue. [1] https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm: s5pc1xx: move SoC to mach-s5pc1xxMinkyu Kang2015-11-30-1448/+0
|/ / | | | | | | | | | | move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-11-22-1/+197
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| * | sunxi: clock: Set AHB1 clock frequency to 200MHz on Allwinner H3Siarhei Siamashka2015-11-22-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz on Allwinner H3 and using PLL6 as the clock source (PLL6/3). This can be verified by reading the value of the AHB1_APB1_CFG_REG register via /dev/mem. It always reads as 0x3180 regardless of the current cpufreq operating point. So this configuration should be safe for use in U-Boot too. PLL6 also needs to be configured before it is used as the clock source, according to the "CCU / Programming Guidelines" section of the Allwinner manual. The current low AHB1 clock speed is limiting the USB transfer speed when booting via FEL. This patch can increase the FEL USB transfer speed from ~510 KB/s to ~950 KB/s. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add H3 DRAM initialization supportJens Kuske2015-11-22-0/+190
| | | | | | | | | | | | | | | | | | | | | | | | Based on existing A23/A33 code and the original H3 boot0. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add basic H3 supportJens Kuske2015-11-22-0/+1
| |/ | | | | | | | | | | | | | | Add initial sun8i H3 support, only uart + mmc are supported for now. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-21-1/+0
|/ | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-11-19-0/+3
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| * ARM: am43xx: Enable QUAD read and EDMA support for ti_qspiVignesh R2015-11-17-0/+3
| | | | | | | | | | | | | | | | | | Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | spl: change return values of spl_*_load_image()Nikita Kiryanov2015-11-18-2/+8
|/ | | | | | | | | | | | | | | | | | | | | | | Make spl_*_load_image() functions return a value instead of hanging if a problem is encountered. This enables main spl code to make the decision whether to hang or not, thus preparing it to support alternative boot devices. Some boot devices (namely nand and spi) do not hang on error. Instead, they return normally and SPL proceeds to boot the contents of the load address. This is considered a bug and is rectified by hanging on error for these devices as well. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-11-16-135/+133
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