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* ARM: rpi_b: power on SDHCI and USB HW modulesStephen Warren2014-01-20-0/+48
| | | | | | | | | | Send RPC commands to the VideoCore to turn on the SDHCI and USB modules. For SDHCI this isn't needed in practice, since the firmware already turned on the power in order to load U-Boot. However, it's best to be explicit. For USB, this is necessary, since the module isn't powered otherwise. This will allow the kernel USB driver to work. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-01-20-24/+0
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| * mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-17-24/+0
| | | | | | | | | | | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-16-1/+14
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| * | arm: rmobile: Add SH QSPI base register addressNobuhiro Iwamatsu2014-01-16-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This adds base register address of SH QSPI. Currently, SH QSPI is used only from R8A7790 and R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-15-1/+12
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| | * mx6: Add initial support for the Hummingboard soloFabio Estevam2014-01-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()Fabio Estevam2014-01-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | usb: ehci: exynos: set/reset hsic physInderpal Singh2014-01-13-0/+14
|/ / | | | | | | | | | | | | | | The controller has 3 ports. The port0 is for USB 2.0 Phy, port1 and port2 are for HSIC phys. The usb 2.0 phy is already being setup. This patch sets up the hsic phys. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-3348/+4495
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * | gpio: zynq: Add dummy gpio routinesJagannadha Sutradharudu Teki2014-01-10-0/+25
| | | | | | | | | | | | | | | | | | | | | GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | armv8: Use __aarch64__ rather than CONFIG_ARM64 in some casesTom Rini2014-01-10-18/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The toolchain sets __aarch64__ for both LE and BE. In the case of posix_types.h we cannot reliably use config.h as that will lead to problems. In the case of byteorder.h it's clearer to check the EB flag being set in either case instead. Cc: David Feng <fenghua@phytium.com.cn> Signed-off-by: Tom Rini <trini@ti.com> Amended by Albert ARIBAUD <albert.u.boot@aribaud.net> to actually remove the config.h include from the posix_types.h files, with permission from Tom Rini.
| * | arm64: core supportDavid Feng2014-01-09-16/+425
| |/ | | | | | | | | | | | | Relocation code based on a patch by Scott Wood, which is: Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Feng <fenghua@phytium.com.cn>
| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-15/+1709
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| | * Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-30-14/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-30-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-30-0/+495
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-30-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-30-0/+837
| | | | | | | | | | | | | | | | | | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-30-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5: Create a common board fileRajeshwari Birje2013-12-30-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-3287/+2164
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| | * arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| | * imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macroOtavio Salvador2014-01-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro allows easy setting in per-pin, as for example: ,---- | imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION); `---- The IOMUX_CONFIG_SION allows for reading PAD value from PSR register. The following quote from the datasheet: ,---- | ... | 28.4.2.2 GPIO Write Mode | The programming sequence for driving output signals should be as follows: | 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need | to read loopback pad value through PSR | 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b). | 3. Write value to data register (GPIO_DR). | ... `---- This fixes the gpio_get_value to properly work when a GPIO is set for output and has no conflicts. Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio Estevam <fabio.estevam@freescale.com> and Eric Bénard <eric@eukrea.com> for helping to properly trace this down. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
| | * mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-02-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * mx6: soc: Staticize set_vddsoc()Fabio Estevam2014-01-02-2/+0
| | | | | | | | | | | | | | | | | | set_vddsoc() is not used anywhere else, so make it static. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2106/+2118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarationsEric Nelson2013-11-13-490/+490
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: remove unused pad declarationsEric Nelson2013-11-13-1043/+0
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/SoloEric Nelson2013-11-13-0/+24
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: remove useless mux/pad declarationsEric Nelson2013-11-13-160/+0
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-1761/+1761
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-0/+45
| | | | | | | | | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | | | | | | | | | | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | | | | | | | | | | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | | | | | | | | | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGAChin Liang See2014-01-09-0/+77
|/ / | | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-12/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * \ Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-11-25-5/+16
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| | * | am335x: fix GPMC config for NAND and NOR SPL bootpekon gupta2013-11-21-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta <pekon@ti.com>
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