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* gpio: Build the da8xx_gpio code for the davinci644x deviceHolger Hans Peter Freyther2013-02-20-1/+7
| | | | | | | The differences include the number of GPIOs and that one is not required to set the pinmux on request. Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-115/+4547
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| * Tegra114: Add arch-tegra114 include filesTom Warren2013-02-11-5/+1365
| | | | | | | | | | | | | | | | | | | | Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * tegra: add SPI SLINK driverAllen Martin2013-02-11-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: add addresses of SPI SLINK controllersAllen Martin2013-02-11-0/+6
| | | | | | | | | | | | | | | | Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: rename FUNCMUX_UART2_UARTBStephen Warren2013-02-11-1/+1
| | | | | | | | | | | | | | | | | | FUNCMUX_ defines should be named after the pin groups they affect, not after the module they're muxing onto those pin groups. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.cTom Warren2013-02-11-4/+73
| | | | | | | | | | | | | | | | | | This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: T20: Remove unused 'SLOW' SoC ID and PLLX table entryTom Warren2013-02-11-1/+0
| | | | | | | | Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Add DDR3 support for AM335x-EVM (Version 1.5A)Jeff Lance2013-02-07-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the DDR3 chip. [Hebbar Gururaja <gururaja.hebbar@ti.com>] - Resolve merge conflict while rebasing. File structure is changed in the mainline. So re-arrange the code accordingly. - Update commit message to reflect the DDR3 part number Signed-off-by: Jeff Lance <j-lance1@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
| * pcm051: Add support for Phytec phyCORE-AM335xLars Poeschel2013-02-07-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board is named pcm051 and has this hardware: SOC: TI AM3359 DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB ETH 1: LAN8710AI SPI-Flash: W25Q64BVSSIG RTC: RV-4162-C7 I2C-EEPROM: CAT32WC32 NAND: MT29F4G08_VFPGA63 PMIC: TPS65910A3 LCD Supported: UART 1 MMC/SD ETH 1 USB I2C SPI Not yet supported: NAND RTC LCD Signed-off-by: Lars Poeschel <poeschel@lemonage.de> [trini: Add #define CONFIG_PHY_ADDR 0 to config] Signed-off-by: Tom Rini <trini@ti.com>
| * am33xx: add a pulldown macro to pinmux configLars Poeschel2013-02-07-1/+2
| | | | | | | | Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
| * ARM: add wfi assembly macroRob Herring2013-02-03-0/+6
| | | | | | | | | | | | | | Since wfi instruction is only available on ARMv7, add a conditional macro for it. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-02-02-12/+1195
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| | * mxs: mmc: Allow overriding default card detect implementationMarek Vasut2013-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some MXS based boards do not implement the card-detect signal. Allow user to specify alternate card-detect implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: ssp: Add SSP registers map for MX23Marek Vasut2013-01-28-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 SSP register layout differs from MX28 in certain bits, adjust the register layout accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: dma: Fix APBH DMA driver for MX23Marek Vasut2013-01-28-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has less channels for the APBH DMA, sligtly different register layout and some bits in those registers are placed differently. Reflect this in the driver. This patch fixes MMC/DMA issue on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: Add MX23 quirks into the clock codeOtavio Salvador2013-01-21-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX23 has different handling of the SSP clock and GPMI NAND clock sources, add necessary quirks into the clock code to properly handle these. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add boot mode descriptionOtavio Salvador2013-01-21-0/+12
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add support on print_cpuinfo()Otavio Salvador2013-01-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add information to identify i.MX23 chips and its known revisions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: ssp: Fix ssp-regs.h for MX23Marek Vasut2013-01-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Disable SSP2 and SSP3 ports on MX23. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add POWER and CLKCTRL register definitionsMarek Vasut2013-01-21-1/+585
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the i.MX23 power control block and clock control block. These are essential for the basic bootstrap of the i.MX23. Also, properly include them in imx-regs.h . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add iomux-mx23.hOtavio Salvador2013-01-21-0/+361
| | | | | | | | | | | | | | | | | | | | | | | | | | | This has been copied from Linux source at revision 786f02b719f. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mx23: Add register base addressesOtavio Salvador2013-01-21-5/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the base addresses of i.MX23 and easy the detection of wrong order in board setup, in case no SoC has been set, an error is raised during build. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: clock: Use 'mxs' prefix for methodsOtavio Salvador2013-01-21-3/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * mxs: ssp: Pull out the SSP bus to regs conversionMarek Vasut2013-01-21-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | tegra: remove IRDA pinmux synonymAllen Martin2013-01-16-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this synonym and replace with UARTB to disambiguate. Signed-off-by: Allen Martin <amartin@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra30: clocks: Fix clock tables for I2C and other periphsTom Warren2013-01-16-0/+4
| | | | | | | | | | | | | | | | | | | | | Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | Tegra30: Add common CPU (shared) filesTom Warren2013-01-16-46/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | Tegra30: Add arch-tegra30 include filesTom Warren2013-01-16-48/+1775
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Common Tegra files are in arch-tegra, shared between T20 and T30. Tegra30-specific headers are in arch-tegra30. Note that some of these will be filled in as more T30 support is added (drivers, WB/LP0 support, etc.). A couple of Tegra20 files were changed to support common headers in arch-tegra, also. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | tegra: display: add board pinmuxMarc Dietrich2013-01-16-3/+4
| |/ | | | | | | | | | | | | | | Boards may require a different pinmux setup for DISPALY than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | arm: Use generic global_dataSimon Glass2013-02-04-37/+1
| | | | | | | | Signed-off-by: Simon Glass <sjg@chromium.org>
* | ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | | | | | | | | | This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move tlb_addr and tlb_size to arch_global_dataSimon Glass2013-02-01-4/+4
| | | | | | | | | | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Address tlb_size in this patch as well] Signed-off-by: Tom Rini <trini@ti.com>
* | ixp: Move timestamp to arch_global_dataSimon Glass2013-02-01-3/+3
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move timer_reset_value to arch_global_dataSimon Glass2013-02-01-4/+1
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move lastinc to arch_global_dataSimon Glass2013-02-01-1/+1
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move tbl to arch_global_dataSimon Glass2013-02-01-1/+1
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move tbu to arch_global_dataSimon Glass2013-02-01-1/+1
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Move timer_rate_hz into arch_global_dataSimon Glass2013-02-01-1/+2
| | | | | | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | at91: Move at91 global data into arch_global_dataSimon Glass2013-02-01-15/+15
| | | | | | | | | | | | Move these fields into arch_global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Add architecture-specific global dataSimon Glass2013-02-01-0/+6
|/ | | | | | | | | | | | | We plan to move architecture-specific data into a separate structure so that we can make the rest of it common. As a first step, create struct arch_global_data to hold these fields. Initially it is empty. This patch applies to all archs at once. I can split it if this is really a pain. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-34/+2
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| * mx31/mx35/mx51/mx53/mx6: add watchdogTroy Kisky2013-01-13-34/+2
| | | | | | | | | | | | | | Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-19/+459
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| * | Exynos: clock: support get_mmc_clk for exynosJaehoon Chung2013-01-11-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | EXYNOS: Add dummy definition to fix compilation dependency on ↵Ajay Kumar2013-01-10-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_EXYNOS_MIPI_DSIM When only DP is used, we need not enable CONFIG_EXYNOS_MIPI_DSIM. But if we do not select CONFIG_EXYNOS_MIPI_DSIM, exynos_fb.c throws error saying exynos_mipi_dsi_init() not defined. So, we add dummy definition for exynos_mipi_dsi_init when CONFIG_EXYNOS_MIPI_DSIM is not defined. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | EXYNOS5: Add support for FIMD and DPAjay Kumar2013-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add panel_info structure required by LCD driver and DP panel platdata for SMDK5250. Add GPIO configuration for LCD. Enable FIMD and DP support on SMDK5250. DP Panel size: 2560x1600. We use 16BPP resolution to get LCD console. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chomium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | EXYNOS5: FDT : Decode peripheral idRajeshwari Shinde2013-01-08-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Api is added to decode peripheral id based on the interrupt number of the peripheral. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | exynos5: Add DT based driver for SMC911X ethernetHatim RV2012-12-26-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree based ethernet driver for SMC911X controller on SMDK5250 boards. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12Chander Kashyap2012-12-26-0/+85
| | | | | | | | | | | | | | | | | | | | | This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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