summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/omap_common.h
Commit message (Collapse)AuthorAgeLines
* DRA7: Add support for ES1.1 silicon ID codeNishanth Menon2014-01-24-0/+1
| | | | | | | | ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALLJassi Brar2014-01-24-1/+0
| | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros2013-12-04-0/+2
| | | | | | | Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: DRA7: Add is_dra7xx cpu check definitionSRICHARAN R2013-12-04-0/+8
| | | | | | | | A generic is_dra7xx cpu check is useful for grouping all the revisions under that. This is used in the subsequent patches. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* usb: dra7xx: Add support for dra7xx xhci USB hostDan Murphy2013-10-20-0/+1
| | | | | | | | | | | Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP5: Add registers and defines for USBOTG SSDan Murphy2013-10-20-0/+4
| | | | | | | Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* omap5: add qspi supportMatt Porter2013-10-07-0/+1
| | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* ARM: OMAP5: Avoid writing into LDO SRAM bitsLokesh Vutla2013-09-20-6/+0
| | | | | | | | | | | Writing magic bits into LDO SRAM was suggested only for OMAP5432 ES1.0. Now these are no longer applicable. Moreover these bits should not be overwritten as they are loaded from EFUSE. So avoid writing into these registers. Boot tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: OMAP4470: Add OMAP4470 identificationTaras Kondratiuk2013-08-28-0/+1
| | | | Signed-off-by: Taras Kondratiuk <taras@ti.com>
* ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-07-26-0/+4
| | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-07-26-0/+4
| | | | | | Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-07-26-0/+2
| | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-13-4/+55
|\ | | | | | | | | | | | | | | | | Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR Conflicts: arch/arm/include/asm/arch-omap5/omap.h Signed-off-by: Tom Rini <trini@ti.com>
| * OMAP5: Enable access to auxclk registersLubomir Popov2013-06-10-0/+4
| | | | | | | | | | | | | | | | | | | | auxclk0 and auxclk1 are utilized on some OMAP5 boards. Define the infrastructure needed for accessing them without using magic numbers. Also remove unrelated TPS62361 defines from clocks.h Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * ARM: DRA7xx: EMIF: Change settings required for EVM boardSricharan R2013-06-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | DRA7 EVM board has the below configuration. Adding the settings for the same here. 2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2 Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: clocks: Update PLL valuesLokesh Vutla2013-06-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc'sLokesh Vutla2013-06-10-0/+8
| | | | | | | | | | | | | | | | Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP5: DRA7xx: support class 0 optimized voltagesNishanth Menon2013-06-10-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | DRA752 now uses AVS Class 0 voltages which are voltages in efuse. This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly. This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: power Add support for tps659038 PMICLokesh Vutla2013-06-10-0/+3
| | | | | | | | | | | | | | | | TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP4+: pmic: Make generic bus init and write functionsLokesh Vutla2013-06-10-0/+3
| | | | | | | | | | | | | | | | | | | | Voltage scaling can be done in two ways: -> Using SR I2C -> Using GP I2C In order to support both, have a function pointer in pmic_data so that we can call as per our requirement. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: OMAP4+: Cleanup header filesLokesh Vutla2013-06-10-3/+1
| | | | | | | | | | | | | | After having the u-boot clean up series, there are many definitions that are unused in header files. Removing all those unused ones. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP3+: introduce generic ABB supportAndrii Tseglytskyi2013-06-10-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptive Body Biasing (ABB) modulates transistor bias voltages dynamically in order to optimize switching speed versus leakage. Adaptive Body-Bias ldos are present for some voltage domains starting with OMAP3630. There are three modes of operation: * Bypass - the default, it just follows the vdd voltage * Foward Body-Bias - applies voltage bias to increase transistor performance at the cost of power. Used to operate safely at high OPPs. * Reverse Body-Bias - applies voltage bias to decrease leakage and save power. Used to save power at lower OPPs. Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
* | am33xx/omap4+: Move SRAM_SCRATCH_SPACE_ADDR to <asm/arch/omap.h>Tom Rini2013-06-06-1/+0
|/ | | | | | | | | | The location of valid scratch space is dependent on SoC, so move that there. On OMAP4+ we continue to use SRAM_SCRATCH_SPACE_ADDR. On am33xx/ti814x we want to use what the ROM defines as "public stack" which is the area after our defined download image space. Correct the comment about and location of CONFIG_SPL_TEXT_BASE. Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP: Cleanup boot parameters usageSRICHARAN R2013-05-10-0/+3
| | | | | | | | | | | The boot parameters are read from individual variables assigned for each of them. This been corrected and now they are stored as a part of the global data 'gd' structure. So read them from 'gd' instead. Signed-off-by: Sricharan R <r.sricharan@ti.com> [trini: Add igep0033 hunk] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: OMAP: Correct save_boot_params and replace with 'C' functionSRICHARAN R2013-05-10-1/+3
| | | | | | | | | | | Currently save_boot_params saves the boot parameters passed from romcode. But this is not stored in a writable location consistently. So the current code would not work for a 'XIP' boot. Change this by saving the boot parameters in 'gd' which is always writable. Also add a 'C' function instead of an assembly code that is more readable. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines commonSRICHARAN R2013-05-10-0/+14
| | | | | | | | These defines are same across OMAP4/5. So move them to omap_common.h. This is required for the patches that follow. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
* arm: dra7xx: Add silicon id support for DRA752 socLokesh Vutla2013-03-11-0/+3
| | | | | | | | Adding CPU detection support for the DRA752 ES1.0 soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: Add control module changesLokesh Vutla2013-03-11-0/+10
| | | | | | | | | | Control module register addresses are changed from OMAP5 to DRA7XX socs. So adding the necessary changes for the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the dplls dataLokesh Vutla2013-03-11-1/+2
| | | | | | | | | | | | A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: dra7xx: clock: Add the prcm changesLokesh Vutla2013-03-11-1/+16
| | | | | | | | PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
* ARM: OMAP5: srcomp: enable slew rate compensation cells after powerupLokesh Vutla2013-03-11-0/+2
| | | | | | | | | | | | | | After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendumSRICHARAN R2013-03-11-1/+5
| | | | | | | | | | | | | | | | | Change OPP settings as per the latest 0.5 version of addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched here to add dummy dividers. While here correcting OPP_NOM mpu, core frequency for OMAP4430 ES2.x Note that OMAP5430 ES1.0 support is still kept alive and would be removed in a cleanup later. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: clock: Add the prcm register changes required for ES2.0SRICHARAN R2013-03-11-0/+4
| | | | | | | | | | | PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain. So adding the nessecary register changes for the same. Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Tom Rini <trini@ti.com>
* ARM: OMAP5: Add silicon id support for ES2.0 revision.SRICHARAN R2013-03-11-0/+2
| | | | | | | | | Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Nishanth Menon <nm@ti.com>
* ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-11-0/+91
| | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Clean up the pmic codeSRICHARAN R2013-03-11-0/+24
| | | | | | | | | | The pmic code is duplicated for OMAP 4 and 5. Instead move the data to Soc specific place and share the code. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Cleanup the clocks layerSRICHARAN R2013-03-11-0/+63
| | | | | | | | | | | | | | | Currently there is quite a lot of code which is duplicated in the clocks code for OMAP 4 and 5 Socs. Avoiding this here by moving the clocks data to a SOC specific place and the sharing the common code. This helps in addition of a new Soc with minimal changes. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4+: Change the PRCM structure prototype common for all SocsSRICHARAN R2013-03-11-0/+304
| | | | | | | | | | | | The current PRCM structure prototype directly matches the hardware register layout. So there is a need to change this for every new silicon revision which has register space changes. Avoiding this by making the prototye generic and populating the register addresses seperately for all Socs. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: SPL: Make spl_mmc.c more genericTom Rini2012-09-27-5/+0
| | | | | | | | Move the default omap/related-centric board_mmc_init to arch/arm/cpu/armv7/omap-common/boot-common.c and move the type defines to <asm/spl.h>. Also use mmc->read_bl_len rather than MMCSD_SECTOR_SIZE Signed-off-by: Tom Rini <trini@ti.com>
* ARM: SPL: Add <asm/spl.h> and <asm/arch/spl.h>Tom Rini2012-09-27-71/+0
| | | | | | | Move the SPL prototypes from <asm/omap_common.h> into <asm/spl.h> and add <asm/arch/spl.h> for arch specific portions of CONFIG_SPL_FRAMEWORK. Signed-off-by: Tom Rini <trini@ti.com>
* ARM: SPL: Remove NAND_MODE_HW_ECC from spl_nand.cTom Rini2012-09-27-1/+0
| | | | | | | This detection code doesn't (and can't) do anything currently, so remove. Signed-off-by: Tom Rini <trini@ti.com>
* ARM: SPL: Rename omap_boot_mode to spl_boot_mode()Tom Rini2012-09-27-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* ARM: SPL: Rename omap_boot_device to spl_boot_deviceTom Rini2012-09-27-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* omap-common: SPL: Add CONFIG_SPL_DISPLAY_PRINT / spl_display_print()Tom Rini2012-09-27-1/+1
| | | | | | | | Only omap4/5 currently have a meaningful set of display text and overo had been adding a function to display nothing. Change how this works to be opt-in and only turned on for omap4/5 now. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct MMC1, remove MMC2 supportTom Rini2012-09-01-1/+1
| | | | | | | | - Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
* OMAP5: ADD chip detection for OMAP5432 SOCLokesh Vutla2012-07-07-0/+1
| | | | | | This patch adds chip detection for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: omap5: correct boot device mode7 for eMMCBalaji T K2012-05-15-1/+4
| | | | | | | In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP4/5: Make the silicon revision variable common.SRICHARAN R2012-05-15-0/+6
| | | | | | | | The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: R Sricharan <r.sricharan@ti.com>
generated by cgit v1.1 at 2024-12-18 04:12:30 +0000