summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/imx-common
Commit message (Collapse)AuthorAgeLines
* arm: imx: add HAB authentication of image to SPL bootSven Ebenfeld2017-01-02-0/+2
| | | | | | | | | | | | | | | | | | | | | When using HAB as secure boot mechanism on Wandboard, the chain of trust breaks immediately after the SPL. As this is not checking the authenticity of the loaded image before jumping to it. The HAB status output will not be implemented in SPL as it adds a lot of strings that are only required in debug cases. With those it exceeds the maximum size of the available OCRAM (69 KiB). The SPL MISC driver support must be enabled, so that the driver can use OTP fuse to check if HAB is enabled. Cc: sbabic@denx.de v2-Changes: None Signed-off-by: Sven Ebenfeld <sven.ebenfeld@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
* imx-common: lcdif: update lcdif regs for i.MX6SL/SLLPeng Fan2016-12-16-3/+4
| | | | | | | Update lcdif regs for i.MX6SL/SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6sll: add iomux settingsPeng Fan2016-12-16-2/+4
| | | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: add i.MX 6SLL CPU typePeng Fan2016-12-16-0/+1
| | | | | | | | Add i.MX6SLL cpu type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: make ipu's di configurableMax Krummenacher2016-11-29-0/+1
| | | | | | | | | The ipu has two display interfaces. Make the used one a parameter in struct display_info_t instead of using unconditionally DI0. DI0 is the default setting. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Eric Nelson <eric@nelint.com>
* arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial supportJagan Teki2016-10-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot Log for i.CoreM6 DualLite/Solo Starter Kit: ----------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 31C Reset cause: POR DRAM: 256 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device switch to partitions #0, OK mmc0 is current device reading boot.scr ** Unable to read file boot.scr ** reading zImage 6741808 bytes read in 341 ms (18.9 MiB/s) Booting from mmc ... reading imx6dl-icore.dtb 30600 bytes read in 19 ms (1.5 MiB/s) Booting using the fdt blob at 0x18000000 Using Device Tree in place at 18000000, end 1800a787 Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 Boot Log for i.CoreM6 Quad/Dual Starter Kit: -------------------------------------------- U-Boot SPL 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46) Trying to boot from MMC1 U-Boot 2016.09-rc2-30739-gd1fa290 (Sep 17 2016 - 00:37:46 +0530) CPU: Freescale i.MX6Q rev1.2 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Reset cause: POR DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* imx-common: enlarge mux width to 4Peng Fan2016-10-04-8/+7
| | | | | | | | For i.MX6, the mux width is 4, not 3. So enlarge the width. IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: iomux: fix snvs usage for i.MX6ULLPeng Fan2016-10-04-3/+3
| | | | | | | | | | | | SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
* imx-common: introduce is_mx6ullPeng Fan2016-10-04-0/+1
| | | | | | | Introduce is_mx6ull macro. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx-common: introduce simpler macros for runtime dectionPeng Fan2016-05-24-0/+8
| | | | | | | | Introduce simpler macros for runtime cpu dection. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-28-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
* imx: imx-common: introduce Resource Domain Controller supportPeng Fan2016-02-21-0/+100
| | | | | | | | | Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-24-2/+2
| | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: apbh_dma: Update APBH-DMA for MX7DPeng Fan2016-01-24-4/+4
| | | | | | | Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-25-1/+1
| | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* video: mxsfb: introduce lcdif_power_downPeng Fan2015-11-12-0/+2
| | | | | | | | | | | | | | | | | | Introudce a new function lcdif_power_down. 1. Waits for a VSYNC interrupt to guarantee the reset is done at the VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?) and helps the LCDIF work normally at the kernel stage. 2. Add power down function to stop lcdif. The reason to introduce lcdif_power_down is that we want lcdif to be in initial state when doing uboot reset or before kernel boot to make system stable, otherwise system may hang. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* imx: lcdif: use one register structure for i.MXesPeng Fan2015-11-12-7/+21
| | | | | | | | | Share one lcdif structure for i.MXes. 1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7 2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: imx-common: move lcdif structure and macro definition to imx-commonPeng Fan2015-11-12-0/+217
| | | | | | | | Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to arch/arm/include/asm/imx-common/regs-lcdif.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: include linux/types.h for regs-common.hPeng Fan2015-11-12-0/+2
| | | | | | | | There are uint8_t, uint32_t types in regs-common.h, so include linux/types.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: hab: add secure boot fuse detailsAdrian Alonso2015-10-30-0/+9
| | | | | | | Add secure boot fuse helper struct to abstract the way to find out secure boot settings per SoC iMX family Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* imx: hab: use unified rom section for mx6sx and mx6ulAdrian Alonso2015-10-30-1/+1
| | | | | | | | | Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target platforms to resolve corresponding HAB_RVT_BASE base address, the RVT table contains pointers to the HAB API functions in ROM code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* imx: hab: rework secure boot support for imx6Adrian Alonso2015-10-30-0/+139
| | | | | | | Rework secure boot support for imx6, move existing hab support for imx6 into imx-common for SoC reuse. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* arm: imx-common: init: rework wdog settings for imx6/imx7Adrian Alonso2015-09-13-0/+1
| | | | | | Rework imx_set_wdog_powerdown to be reused by imx6 and imx7 Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* imx: imx7d: Add SoC system supportAdrian Alonso2015-09-13-0/+21
| | | | | | | | | Add imx7d basic SoC system support Misc arch dependent functions for system bring up Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: system counter driver for imx7d and mx6ulAdrian Alonso2015-09-13-0/+29
| | | | | | | | | | Add system counter driver for imx7d and mx6ul imx7 and imx6ul supports system counter timer as well as GPT timer (arch/arm/imx-common/timer.c); The default for imx7 is systemcounter timer. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* arm: imx: imx-common: init: move arch init common setupAdrian Alonso2015-09-13-0/+3
| | | | | | | | Move common imx6 arch init setup, init.c can be extended and reused to support imx7 SoC keeping init arch common code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* imx: arch-mx6: add is_soc_type helper macroAdrian Alonso2015-09-13-0/+3
| | | | | | Add helper macro is_soc_type to identify iMX SoC family Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* imx: iomux-v3: add imx7d support for iomuxcAdrian Alonso2015-09-02-0/+32
| | | | | | | | | | | | | | | * Add imx7d support for iomux controller * imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsr IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings for iomuxc-lpsr pads. * Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx-common: consolidate macros and prototypes into sys_proto.hPeng Fan2015-09-02-0/+46
| | | | | | | | | | | | | | | | | Move most macro definitions and prototypes into "arch/arm/include/asm/imx-common/sys_proto.h" to avoid duplicated function prototypes and marco definitions for different i.MX SoCs. This patch do not remove the sys_proto.h for different i.MX SoCs, because we need to modify lots of driver code and others. This patch remove duplicated macros and prototypes and incude "sys_proto.h" of imx-common for each sys_proto.h of different i.MX platforms. Then later we should avoid add stuff in sys_proto.h of each platform, and modify driver to include common sys_proto.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
* imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-02-0/+4
| | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-0/+2
| | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* dm: gpio: vf610: Add GPIO driver supportBhuvanchandra DV2015-06-08-0/+6
| | | | | | Add GPIO driver support to Freescale VF610 Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
* imx: dma: correct MXS_DMA_ALIGNMENTPeng Fan2015-05-26-1/+1
| | | | | | | | | | | | | | | | We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* i2c: mxc: refactor i2c driver and support dmPeng Fan2015-05-14-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Introduce a new structure `struct mxc_i2c_bus`, this structure will used for non-DM and DM. 2. Remove `struct mxc_i2c_regs` structure, but use register offset to access registers based on `base` entry of `struct mxc_i2c_bus`. 3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform flags. A new flag is introduced, I2C_QUIRK_FLAG. 4. Most functions use `struct mxc_i2c_bus` as one of the parameters. Make most functions common to DM and non-DM, try to avoid duplicated code. 5. Support DM, but pinctrl is not included. Pinmux setting is still set by setup_i2c, but we do not need bus_i2c_init for DM. 6. struct i2c_parms and struct sram_data are removed. 7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist paramter of bus_i2c_init is modified to i2c index. Add new prototype i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus. Board file take the responsibility to implement this function, like this: " int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) { if (i2c_bus->index == 0) force_bus_idle(i2c_pads_info0); else if (i2c_bus->index == 1) force_bus_idle(i2c_pads_info1); else xxxxxx } " 8. Introduce a weak function, enable_i2c_clk 9. Tested on an i.MX7 platform. Log info: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ ] |-- soc simple_bus [ ] | |-- aips-bus@30000000 simple_bus [ ] | | |-- anatop@30360000 simple_bus [ ] | | `-- snvs@30370000 simple_bus [ ] | |-- aips-bus@30400000 simple_bus [ ] | `-- aips-bus@30800000 i2c [ ] | |-- i2c@30a20000 i2c [ ] | `-- i2c@30a40000 simple_bus [ ] `-- regulators => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 08 50 => i2c md 8 31 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* usb: host: Add ehci-vf USB driver for ARM Vybrid SoC'sSanchayan Maity2015-04-23-0/+26
| | | | | | | This driver adds support for the USB peripheral on Freescale Vybrid SoC's. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* video, ipu: make ldb clock frequency overwritable through board codeHeiko Schocher2015-04-20-0/+1
| | | | | | | | | | the ldb clock can be setup in board code (for example set through PLL5). Update the ldb_clock rate also through board code. This should be removed, if a clock framework is availiable. Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-05-0/+5
|\
| * imx: mx6 sabreauto: Add board support for USB EHCIYe.Li2014-11-03-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-27-0/+22
|\ \ | |/
| * ARM: i.MX video: declare displays and display_count publiclyEric Nelson2014-10-21-0/+5
| | | | | | | | | | | | | | | | Declare displays[] and display_count in imx-common/video.h to prevent "Should it be static?" messages when compiling board files with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * ARM: i.MX: provide declaration for board_spi_cs_gpioEric Nelson2014-10-21-0/+17
| | | | | | | | | | | | | | | | Provide a public declaration of the board_spi_cs_gpio() callback for i.MX SPI chip selects to prevent the warning "Should it be static?" when compiling with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | imx: Add error checking to setup_i2c()Simon Glass2014-10-22-2/+2
|/ | | | | | | Since this function can fail, check its return value. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
* vf610twr: Tune DDR initialization settingsAnthony Felice2014-10-07-0/+2
| | | | | | | | | | | | | | | Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice <tony.felice@timesys.com> [rebased on v2014.10-rc2] Signed-off-by: Stefan Agner <stefan@agner.ch>
* i2c: imx: add macros to setup pads for multiple SoC typesNikita Kiryanov2014-09-09-0/+33
| | | | | | | | | | | | Add macro which defines i2c_pads_info structs for multiple SoC types, and a macro which selects the appropriate struct based on CPU type, thus eliminating the need to manage multiple i2c pad configurations manually when supporting multiple SoC types. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: vf610: add NFC pin muxStefan Agner2014-08-30-0/+4
| | | | | | | | Add pin mux for NAND Flash Controller (NFC). NAND can be connected using 8 or 16 data lines, this patch adds pin mux entries for all 16 data lines. Signed-off-by: Stefan Agner <stefan@agner.ch>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-0/+25
|\
| * imx: iomux: add macros to setup iomux for multiple SoC typesTim Harvey2014-06-06-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list and add macros for declaring the pad_list that take into account the SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL iomux). Cc: Stefan Roese <sr@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Andy Ng <andreas2025@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Tapani Utriainen <tapani@technexion.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | arm: imx: Add two macros for VF610 in IOMUX_PAD structureAlison Wang2014-06-09-0/+2
|/ | | | | | | Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in IOMUX_PAD structure. Signed-off-by: Alison Wang <Huan.Wang@freescale.com>
* iomux-v3: Add support for mx6sl LVE bitFabio Estevam2014-05-09-0/+5
| | | | | | | | | | | | | On mx6sl there is a LVE (Low Voltage Enable) bit in the IOMUXC_SW_PAD_CTL register that can enable or disable low voltage on the pad. LVE is bit 22 of IOMUXC_SW_PAD_CTL register, but in order to make the calculation easier we can define it as a flag in bit 1, since this bit is unused. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Otavio Salvador <otavio@ossystems.com.br>
generated by cgit v1.1 at 2024-11-20 13:44:50 +0000