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* ARM: zynq: Remove spl.hMichal Simek2014-08-19-16/+0
| | | | | | | | Do not specify own zynq specific SPL macros because there is no need for that. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: zynq: Move ps7_init() out of spl.hMichal Simek2014-08-19-2/+2
| | | | | | | Prepare for spl.h removal. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+2
| | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Add MIO detection codeMichal Simek2014-05-14-0/+1
| | | | | | | Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Fix bootmode maskMike Looijmans2014-05-14-1/+1
| | | | | | | | | | | Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: Added efuse status register base addressSiva Durga Prasad Paladugu2014-05-14-0/+10
| | | | | | | | | | Added efuse status register base address. This register is used for determining whether efuse was blown or not. Also, added the zynq_get_silicon_version() to get the silicon version of the zynq board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* mmc: zynq: Add OF initialization supportMichal Simek2014-03-04-0/+1
| | | | | | Enable initialize sdhci from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Add support for U-BOOT SPLMichal Simek2014-02-19-0/+18
| | | | | | | | | | | | | | | | | SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-1/+1
| | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-1/+1
| | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Provide a framework to read clock frequenciesSoren Brinkmann2014-02-19-2/+59
| | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: serial: Simplify serial driver initializationMichal Simek2014-02-19-0/+2
| | | | | | | | | | Define both serial uarts in the driver and return default uart based on board configuration. - Move baseaddresses to hardware.h - Define default baudrate and clock values Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Move bootmode to headersMichal Simek2014-02-19-0/+6
| | | | | | These numbers will be reused by SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* gpio: zynq: Add dummy gpio routinesJagannadha Sutradharudu Teki2014-01-10-0/+25
| | | | | | | GPIO dummy routines are required for fdt build, may be removed these dependencies once the u-boot fdt is fully optimized. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* zynq: Add support to find bootmodeJagannadha Sutradharudu Teki2014-01-10-0/+1
| | | | | | | | | | | Added support to find the bootmodes by reading slcr bootmode register. this can be helpful to autoboot the configurations w.r.t a specified bootmode. Added this functionality on board_late_init as it's not needed for normal initializtion part. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'Albert ARIBAUD2013-09-03-0/+9
|\ | | | | | | | | | | | | Conflicts: arch/arm/include/asm/arch-zynq/hardware.h The conflict above was trivial and solved during merge.
| * zynq: Add new ddrc driver for ECC supportMichal Simek2013-08-12-0/+9
| | | | | | | | | | | | | | | | | | | | The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB. Also u-boot should report only the half size of memory. Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | spi: Add zynq spi controller driverJagannadha Sutradharudu Teki2013-08-07-0/+2
|/ | | | | | | | | Zynq spi controller driver supports 2 buses and 3 chipselects on each bus. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-34/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-2/+11
| | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* i2c: zynq: Add support for Xilinx ZynqMichal Simek2013-04-30-0/+2
| | | | | | | | | Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* mmc: Add support for Xilinx Zynq sdhci controllerMichal Simek2013-04-30-0/+5
| | | | | | | Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Move macros to hardware.hMichal Simek2013-04-30-0/+2
| | | | | | | | Add all fixed addresses to hardware.h and change petalinux configuration to support this. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-1/+7
| | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Move scutimer baseaddr to hardware.hMichal Simek2013-04-30-0/+1
| | | | | | | | Move baseaddr to hardware.h to be shared between configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addressesMichal Simek2013-04-30-6/+6
| | | | | | | | XPSS prefix was used in past and it is obsolete for quite some time. Let's use correct SoC name which is Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: Add lowlevel initialization to CMichal Simek2013-02-07-1/+45
| | | | | | | Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: zynq: Add SLCR support with system resetMichal Simek2013-02-07-0/+71
The patch provides slcr base address initialization support and a support to reset the cpu through slcr driver, hence removed the reset_cpu() from board.c. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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