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* sunxi: usbc: Add support for usb0 to the common usbc codeHans de Goede2015-01-14-1/+5
| | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otgHans de Goede2015-01-14-3/+24
| | | | | | | | | | Most of the usb-controller init code found in ehci-sunxi.c also is necessary to init the otg usb controller, so move it to a common place. While at it also update various #ifdefs / defines for sun8i support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Add lvds supportHans de Goede2015-01-14-0/+15
| | | | | | | Add support for lvds lcd panels Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add VGA output supportHans de Goede2015-01-14-0/+78
| | | | | | | Add support for VGA directly from the sunxi SoC / display engine. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Add lcd output supportHans de Goede2015-01-14-6/+26
| | | | | | | | Add lcd output support, see the new Kconfig entries and doc/README.video for how to enable / configure this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1Hans de Goede2015-01-14-0/+2
| | | | | | | | | | | | | Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a preparation patch for adding lcd support. While at it also swap the divider search order, searching from low to high, as the comment above the code says we should do. In cases where there are multiple solutions this will result in picking a lower pll clock and divider, which is more stable and saves power. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Add support for gpio pins on the AXP209 pmicHans de Goede2015-01-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino board, which uses gpio0 of the axp209 for the lcd-power signal. This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c changes are universal, adding gpio support for the other AXP pmics (when necessary) should be a matter of adding the necessary axp_gpio_foo functions to their resp. drivers, and add "#define AXP_GPIO" to their header file. Note this commit only adds support for the non device-model version of the gpio code, patches for adding support to the device-model version are very welcome. The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix is there in case we need to support gpio-s on more then 1 pmic in the future. At least A80 boards have 2 pmics, and we may end up needing to support gpio-s on both. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: gpio: Properly sort mux defines by port numberHans de Goede2015-01-14-5/+5
| | | | | | | | Move a few mux defines around so that all the mux defines are properly sorted by port number. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Set input sync enableHans de Goede2015-01-14-0/+1
| | | | | | | | | | | | | | | | | | | Add a write to the "unknown" (*) register to enable auto input sync, when initially adding sunxi hdmi output support this magic write from the android kernel code was missed, causing lcdc -> hdmi encoder sync problems. With this write added, we can drop the modesetting retries and the extra delays added to work around these sync problems. With the retries dropped there also is no need to 0 all the enable flags at the beginning of the modeset, as they are initialized to 0 already by engines_init. *) "unknown" is the actual name of this register in the android kernel sources Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add hdmi supportHans de Goede2015-01-14-10/+23
| | | | | | | | | | | | | | | | | So far we've been programming the hdmi-encoder to send out dvi data over the hdmi connector. This works well for most devices, including hdmi devices, but not all devices accept dvi data on a hdmi input. Add support for sending proper hdmi data over the hdmi output found on most sunxi boards. This can be turned on by adding monitor=hdmi as option to the video-mode env. variable. A follow up patch will determine whether to send dvi or hdmi automatically when EDID is used. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: video: Add DDC & EDID supportHans de Goede2015-01-14-0/+85
| | | | | | | | | | Add DDC & EDID support and use it to automatically select the native mode of the attached monitor. This can be disabled by adding edid=0 as option to the video-mode env. variable. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* sunxi: Fix PLL1 running at half speed on sun8iHans de Goede2015-01-14-1/+1
| | | | | | | | | | PLL1 on sun6i / sun8i also has a p factor which divides the clock by 2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is used and we were setting it to 1, resulting in the CPU running at 504 MHz instead of 1008 MHz, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fix buggy sun6i/sun8i DRAM size detection logicSiarhei Siamashka2015-01-14-16/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After reboot, reset or even short power off, DRAM typically retains the old stale data for some period of time (for this type of memory, the bits of data are stored in slowly discharging capacitors). The current sun6i/sun8i DRAM size detection logic, which is inherited from the Allwinner code, relies on using a large magic signature with the hope that it is unique enough and unlikely to ever accidentally match this leftover garbage data in RAM. But this approach is inherently unsafe, as can be demonstrated using the following test program: /***** A testcase for reproducing the problem ******/ void main(int argc, char *argv[]) { size_t size, i; uint32_t *buf; /* Allocate the buffer */ if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) || !(buf = malloc(size))) { printf("Need buffer size in MiB as a cmdline argument\n"); exit(1); } /* Fill it with the Allwinner DRAM "magic" values */ for (i = 0; i < size / 4; i++) buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64; /* Try to reboot */ system("reboot"); /* And wait */ for (;;) {} } /***************************************************/ If this test program is run on the device (giving it a large chunk of memory), then the DRAM size detection logic in u-boot gets confused after reboot and fails to initialize DRAM properly. A better approach is not to rely on luck and abstain from making any assumptions about the properties of the leftover garbage data in RAM. Instead just use a more reliable code for testing whether two different addresses refer to the same memory location. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sun8i: Add dram initialization supportHans de Goede2015-01-14-0/+272
| | | | | | | | Based on the register / dram_para headers from the Allwinner u-boot / linux sources + the init sequences from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Use memcmp for mctl_mem_matchesHans de Goede2015-01-14-9/+3
| | | | | | | Use memcmp for mctl_mem_matches instead of DIY. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Fill memory before comparing it when doing dram init on sun6iHans de Goede2015-01-14-0/+29
| | | | | | | | | | | | | | | | | | | The sun8i boot0 code fills the DRAM with a "random" pattern before comparing it at different offsets to do columns, etc. detection. The sun6i boot0 code does not do it, instead relying on the memory contents being random enough to begin with for the memcmp to properly detect the wrap-around address, iow it is working purely by chance. Since our sun6i dram code was modelled after the boot0 code it contained the same issue. This commit fixes this by filling the memory with a unique, distinct pattern. The new mctl_mem_fill function this introduces is added as an inline helper in dram.h, so that it can be shared with the sun8i dram code. While at it move mctl_mem_matches to dram.h for re-use in sun8i too. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Move await_completion dram helper to dram.hHans de Goede2015-01-14-0/+14
| | | | | | | | | The await_completion helper is already copy pasted between the sun4i and sun6i dram code, and we need it for sun8i too, so lets make it an inline helper in dram.h, rather then adding yet another copy. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()Hans de Goede2015-01-14-1/+5
| | | | | | | | The sun8i dram code sometimes wants to enable sigma delta mode, add a parameter to allow this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add support for the rsb (Reduced Serial Bus)Hans de Goede2015-01-14-1/+60
| | | | | | | | | | | | sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/Hans de Goede2015-01-14-3/+3
| | | | | | | | The p2wi interface is only available on sun6i, adjust the gpio pinmux and base address defines for it to reflect this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add sunxi_get_sid helper functionHans de Goede2015-01-14-0/+1
| | | | | | | | | | On sun6i the SID is stored in the pmic, rather then in the SoC itself, add a helper function to abstract this away. This makes our MAC address generation code also work on sun6i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: mmc: Properly setup mod-clk and clock sampling phasesHans de Goede2015-01-14-9/+15
| | | | | | | | | | | | | | | | | | | | | | | The sunxi mmc controller has both an internal clock divider, as well as the divider in the mod0-clk for the mmc controller. The internal divider cannot be used, as it conflicts with the setting of clock sampling phases which is done in the mod0-clk, so it must be set to 0 (divide by 1). For some reason while the kernel has had this correct from day one, the u-boot sunxi mmc code has been using a fixed mod0-clk and setting its internal divider depending on the desired speed. This is something which we've inherited from the original Allwinner u-boot sources, but while this has been fixed in Allwinner's own u-boot code at least for the A23 and later upstream u-boot was still doing this wrong. This commit fixes this, thereby also fixing mmc support not working reliable on the A23 (which seems more sensitive to this) and possible also fixes some other sunxi mmc issues. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add sunxi_get_ss_bonding_id() functionHans de Goede2015-01-14-1/+8
| | | | | | | | Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between the A31s and the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add gmac support for sun6i boardsHans de Goede2014-11-25-0/+13
| | | | | | | Hookup the gmac found on the sun6i / A31 SoCs. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: video: Add simplefb supportLuc Verhaegen2014-11-25-0/+2
| | | | | | | | | | | | Add simplefb support, note this depends on the kernel having support for the clocks property which has recently been added to the simplefb devicetree binding. Signed-off-by: Luc Verhaegen <libv@skynet.be> [hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as disussed on the devicetree list] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>.
* sunxi: video: Add cfb console driver for sunxiLuc Verhaegen2014-11-25-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | This adds a fixed mode hdmi driver for the sunxi platform. The fixed mode is a relatively safe 1024x768, more complete EDID handling is currently not provided. Only HDMI is supported today. This code is enabled when HPD detects an attached monitor. Current config is such that 8MB is shaved off at the top of the RAM. This avoids several memory handling issues, most significant is the fact that on linux on ARM you are not allowed to remap known RAM as IO. A clued in display driver will be able to recycle this reserved RAM in future though. cfbconsole was chosen as it provides the most important functionality: a working u-boot console, allowing for the debugging of certain issues without the need for a UART. Signed-off-by: Luc Verhaegen <libv@skynet.be> [hdegoede@redhat.com: Major cleanups and some small bugfixes] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add video pll clock functionsHans de Goede2014-11-25-1/+105
| | | | | | | This is a preparation patch for adding support for HDMI out. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun4i: Rename dram_clk_cfg to dram_clk_gateHans de Goede2014-11-25-1/+1
| | | | | | | | | The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on sun6i, so name it the same on sun4i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: ehci: Add sun6i ehci supportHans de Goede2014-11-13-0/+22
| | | | | | | | Add support for the 2 ehci controllers found on the sun6i (A31) soc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Marek Vasut <marex@denx.de>
* sun6i: Add dram initialization codeHans de Goede2014-11-13-3/+368
| | | | | | | | | | | | Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.). This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun4i: Rename dram files to dram_sun4i.xHans de Goede2014-11-13-165/+184
| | | | | | | In preparation for adding sun6i dram support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add cpucfg register definitionsHans de Goede2014-11-13-1/+69
| | | | | | | Not used atm, for future use (e.g. PSCI). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add clock functions needed for SPL / DRAM initHans de Goede2014-11-13-1/+28
| | | | | | | | | | Add clock_init_safe and clockset_pll5 functions, as these are needed for SPL support resp. DRAM init (which is needed for SPL too). Also add some extra clock register constant defines. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sun6i: Add new p2wi controller driverOliver Schinagl2014-11-13-0/+143
| | | | | | | | | | | The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* dm: sunxi: Add pinmux functions which take a bank parameterSimon Glass2014-11-05-1/+3
| | | | | | | | | | With driver model we will have access to a bank pointer, so we want to use it rather than converting back to a number, and then back to a bank pointer. Add functions to provide this feature. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?IIan Campbell2014-11-05-6/+6
| | | | | | | | | | | Mostly automatic with: sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I) followed by removing the relevant #defines from include/configs/sun?i.h by hand. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add clock_get_pll5p() functionHans de Goede2014-10-24-0/+4
| | | | | | | | This is a preparation patch for making the pll5 "p" divisor configurable through Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add support for using R_UART as consoleChen-Yu Tsai2014-10-24-0/+4
| | | | | | | | | | The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads. Add support for R_UART so we can have a console while using mmc. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Allow specifying module in prcm apb0 init functionChen-Yu Tsai2014-10-24-1/+1
| | | | | | | | | The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add support for R_PIO gpio banksHans de Goede2014-10-24-2/+29
| | | | | | | | | | | | | | | The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond. Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add basic A23 supportChen-Yu Tsai2014-10-24-1/+1
| | | | | | | | | | | The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup. There is no SPL support for A23, as we do not have any documentation or sample code for DRAM initialization. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mmc: sunxi: Add support for sun8i (A23)Chen-Yu Tsai2014-10-24-1/+1
| | | | | | | | | | The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i. Re-use code added for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Add sun8i (A23) UART0 pin mux supportChen-Yu Tsai2014-10-24-0/+6
| | | | | | | UART0 pin muxes on the A23 have a different function value. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Fix reset command on sun6i/sun8iChen-Yu Tsai2014-10-24-0/+20
| | | | | | | | | | The watchdog on sun6i/sun8i has a different layout. Add the new layout and fix up the setup functions so that reset works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk> [ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
* ARM: sunxi: Add sun6i/sun8i timer block register definitionChen-Yu Tsai2014-10-24-0/+6
| | | | | | | | | | | The RTC hardware has been moved out of the timer block on sun6i/sun8i. In addition, there are more watchdogs available. Also note that the timer block definition is not completely accurate for sun5i/sun7i. Various blocks are missing or have been moved out. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi: Move watchdog register definitions to separate fileChen-Yu Tsai2014-10-24-14/+27
| | | | | | | | | | | | On later Allwinner SoCs, the watchdog hardware is by all means a separate hardware block, with its own address range and interrupt line. Move the register definitions to a separate file to facilitate supporting newer SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Use PG3 - PG8 as io-pins for mmc1Hans de Goede2014-10-24-0/+2
| | | | | | | | | | None of the known sunxi devices actually use mmc1 routed through PH, where as some devices do actually use mmc1 routed through PG, so change the routing of mmc1 to PG. If in the future we encounter devices with mmc1 routed through PH, we will need to change things to be a bit more flexible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: When we've both mmc0 and mmc2, detect from which one we're bootingHans de Goede2014-10-24-1/+1
| | | | | | | | | | | | | sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're booting, and make that one "mmc dev 0" so that a single u-boot binary can be used for both the onboard eMMC and for external sdcards. When we're booting from mmc2, we make it dev 0 because that is where the SPL will load the tertiary payload (the actual u-boot binary in our case) from, see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sun6i: Define UART0 pins for A31Chen-Yu Tsai2014-10-24-0/+3
| | | | | | | UART0 is the default debug/console UART on the A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: sunxi-mmc: Add mmc support for sun6i / A31Hans de Goede2014-10-24-1/+4
| | | | | | | | | | | The mmc hardware on sun6i has an extra reset control that needs to be de-asserted prior to usage. Also the FIFO address is different. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [wens@csie.org: use setbits_le32 for reset control, drop obsolete changes, rewrite different FIFO address handling, add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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