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* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-21-0/+17
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Tidy up the register-access macrosSimon Glass2016-01-21-3/+4
| | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a video-output driverSimon Glass2016-01-21-0/+349
| | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-21-0/+636
| | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-21-0/+456
| | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-21-29/+29
| | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-21-0/+41
| | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clock: Add a function to find a clock by IDSimon Glass2016-01-21-0/+12
| | | | | | | | The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-21-4/+8
| | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: add rk3036 sdram driverhuang lin2015-12-01-0/+341
| | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add early uart driverhuang lin2015-12-01-0/+44
| | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add header files for GRFhuang lin2015-12-01-0/+493
| | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add clock driverhuang lin2015-12-01-0/+168
| | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: add timer driverhuang lin2015-12-01-0/+22
| | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Add SPI driverSimon Glass2015-09-02-0/+20
| | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add I2C driverSimon Glass2015-09-02-0/+70
| | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add SDRAM initSimon Glass2015-09-02-0/+576
| | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add header files for PMU and GRFSimon Glass2015-09-02-0/+857
| | | | | | | PMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add clock driverSimon Glass2015-09-02-0/+185
| | | | | | | Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add basic peripheral and clock definitionsSimon Glass2015-09-02-0/+119
| | | | | | | | Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-02-0/+28
This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
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