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* board: ti: OMAP5: added USB initializtion codeKishon Vijay Abraham I2015-08-28-0/+6
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in omap5 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: beagle_x15: added USB initializtion codeKishon Vijay Abraham I2015-08-28-1/+1
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in beagle_x15 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-28-0/+3
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-28-0/+6
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-28-0/+1
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspiVignesh R2015-08-17-0/+5
| | | | | | | | | | | Enable TI_EDMA3 and SPL_DMA support, so as to reduce boot time. With DMA enabled there is almost 3x improvement in read performance. This helps in reducing boot time in qspiboot mode Also add EDMA3 base address for DRA7XX and AM57XX. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ARM: DRA7/ OMAP5: implement Auxiliary Control Register configurationNishanth Menon2015-08-12-0/+1
| | | | | | | | | | Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: Richard Woodruff <r-woodruff2@ti.com> Suggested-by: Brad Griffis <bgriffis@ti.com> Reviewed-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* omap: SPL boot devices cleanup and completionPaul Kocialkowski2015-07-27-10/+13
| | | | | | | This cleans up the SPL boot devices for omap platforms and introduces support for missing boot devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Common boot code OMAP3 support and cleanupPaul Kocialkowski2015-07-27-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces OMAP3 support for the common omap boot code, as well as a major cleanup of the common omap boot code. First, the omap_boot_parameters structure becomes platform-specific, since its definition differs a bit across omap platforms. The offsets are removed as well since it is U-Boot's coding style to use structures for mapping such kind of data (in the sense that it is similar to registers). It is correct to assume that romcode structure encoding is the same as U-Boot, given the description of these structures in the TRMs. The original address provided by the bootrom is passed to the U-Boot binary instead of a duplicate of the structure stored in global data. This allows to have only the relevant (boot device and mode) information stored in global data. It is also expected that the address where the bootrom stores that information is not overridden by the U-Boot SPL or U-Boot. The save_omap_boot_params is expected to handle all special cases where the data provided by the bootrom cannot be used as-is, so that spl_boot_device and spl_boot_mode only return the data from global data. All of this is only relevant when the U-Boot SPL is used. In cases it is not, save_boot_params should fallback to its weak (or board-specific) definition. save_omap_boot_params should not be called in that context either. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* ARM: DRA7: CPSW: Remove IO delay hackLokesh Vutla2015-06-12-25/+0
| | | | | | | | Now all manual mode configurations are done as part of IO delay recalibration sequence, remove the hack done for CPSW. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Add support for manual mode configurationLokesh Vutla2015-06-12-1/+40
| | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "manual mode" also programmed, when predefined delay characteristics cannot be used for the interface. struct iodelay_cfg_entry is introduced for populating manual mode IO timings. For configuring manual mode, along with the normal pad configuration do the following steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux) - Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL. And pass the offset of the CFG_XXX register in iodelay_cfg_entry. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Add support for IO delay configurationLokesh Vutla2015-06-12-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7, in addition to the regular muxing of pins, an additional hardware module called IODelay which is also expected to be configured. This "IODelay" module has it's own register space that is independent of the control module. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay recalibration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do muxing as part of IOdelay recalibration. IODELAY recalibration sequence: - Complete AVS voltage change on VDD_CORE_L - Unlock IODLAY config registers. - Perform IO delay calibration with predefined values. - Isolate all the IOs - Update the delay mechanism for each IO with new calibrated values. - Configure PAD configuration registers - De-isolate all the IOs. - Relock IODELAY config registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Add support for virtual mode configurationLokesh Vutla2015-06-12-0/+20
| | | | | | | | | | | | | | | | | | | In addition to the regular mux configuration, certain pins of DRA7 require to have "virtual mode" also programmed. This allows for predefined delay characteristics to be used by the SoC to meet timing characterstics needed for the interface. Provide easy to use macro to do the same. For configuring virtual mode, along with normal pad configuration add the following two steps: - Select MODESELECT field of each assocaited PAD. CTRL_CORE_PAD_XXX[8]:MODESELECT = 1 - DELAYMODE filed should be configured with value given in DATA Manual. CTRL_CORE_PAD_XXX[7:4]:DELAYMODE =[0-15] (as given in DATA manual). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Add pinctrl register definitionsLokesh Vutla2015-06-12-0/+15
| | | | | | | | | | Adopting the pinctrl register definitions from Linux kernel to be consistent. Old definitions will be removed once all the pinctrl data is adapted to new definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: DRA7: Make do_set_mux32() genericLokesh Vutla2015-06-12-0/+1
| | | | | | | | | do_set_mux32() is redefined in dra7xx and beagle_x15 boards. IO delay recalibration sequence also needs this. Making it generic to avoid duplication. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* board: ti: DRA7: added USB initializtion codeKishon Vijay Abraham I2015-04-14-0/+12
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in dra7xx board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao2015-03-13-0/+3
| | | | | | | | | | | | | | | | | | | This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: DRA7xx: Add support for power rail groupingLubomir Popov2015-01-29-3/+17
| | | | | | | | | | | | | | | | | | | | | | On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC core rails. This concept of using one SMPS to supply multiple core domains (in various, although limited combinations, per primary device use case) has now become common and is used by many customer J6/J6Eco designs; it is supported by a number of corresponding PMIC OTP versions. This patch implements correct operation of the core voltages scaling routine by ensuring that each SMPS that is supplying more than one domain shall be written only once, and with the highest voltage of those fused in the SoC (or of those defined in the corresponding header if fuse read is disabled or fails) for the power rails belonging to the group. The patch also replaces some PMIC-related magic numbers with the appropriate definitions. The default OPP_NOM voltages for the DRA7xx SoCs are updated as well, per the latest DMs. Signed-off-by: Lubomir Popov <l-popov@ti.com>
* arm: omap: add support for am57xx devicesFelipe Balbi2014-12-04-3/+3
| | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: omap5: tps659038: rename regulator definesFelipe Balbi2014-12-04-5/+5
| | | | | | | | | Those regulators don't have any coupling with what they supply, so remove the suffixes in order to not confuse anybody. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* board/ti/dra7xx: add support for parallel NORpekon gupta2014-08-25-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
* armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_contextTom Rini2014-05-23-54/+1
| | | | | | | | | | | | | The omap_hw_init_context function (and assorted helpers) is the same for all OMAP-derived parts as when CHSETTINGS are used, that's the same and our DDR base is also always the same. In order to make this common we simply need to update the names of the define for DDR address space which is also common. Cc: Sricharan R. <r.sricharan@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA72x: Add Silicon ID supportLokesh Vutla2014-05-23-0/+1
| | | | | | | Add silicon ID code for DRA722 silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
* ARM: omap5: add platform specific info for GPMC and ELM controllerspekon gupta2014-05-23-6/+90
| | | | | | | | | | | | | | | | This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
* ARM: OMAP5: add CKO buffer control maskDmitry Lifshitz2014-05-13-0/+3
| | | | | | Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
* ARM: OMAP5: add UART4 supportDmitry Lifshitz2014-05-13-0/+1
| | | | | | Add UART4 base address. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
* ARM: OMAP: hide custom bit manipulation function sr32()Wolfgang Denk2014-04-17-1/+0
| | | | | | | | | | The only remaining user of the custom bit manipulation function sr32() is arch/arm/cpu/armv7/omap3/clock.c, so make it a static function in that file to prepare complete removal. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* spl: Fix guardian macros in spl.hMarek Vasut2014-03-28-1/+1
| | | | | | | | | Fix the macros guarding the spl.h header for various platforms. Due to a typo and a propagation of it, the macros went out-of-sync with their ifdef check, so fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
* mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-04-1/+1
| | | | | | | | | omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
* mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers ↵pekon gupta2014-03-04-45/+1
| | | | | | | | | | | | | | | into common omap_gpmc.h Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related defines and declarations scattered in SoC platform specific header files like include/asm/arch-xx/cpu.h However, GPMC hardware remains same across all platforms thus this patch merges GPMC data scattered across different arch-xx specific header files into single header file include/asm/arch/omap_gpmc.h Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
* ARM: O5/dra7xx: Add SATA boot supportDan Murphy2014-02-19-9/+1
| | | | | | | | | | | | | Add the SATA boot support for OMAP5 and dra7xx. Renamed the omap_sata_init to the common init_sata(int dev) for commonality in with sata stack. Added the ROM boot device ID for SATA. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* DRA7: add ABB setup for MPU voltage domainNishanth Menon2014-01-24-0/+2
| | | | | | | | | Patch adds modification to shared omap5 abb_setup() function, and proper registers definitions needed for ABB setup sequence. ABB is initialized for MPU voltage domain at OPP_NOM. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* DRA7: Add support for ES1.1 silicon ID codeNishanth Menon2014-01-24-0/+1
| | | | | | | | ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support for ES1.1 IDCODE change. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ARM: OMAP4/5: Remove dead code against CONFIG_SYS_ENABLE_PADS_ALLJassi Brar2014-01-24-1/+0
| | | | | | | | | The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* ARM: OMAP5: Add SATA platform glueRoger Quadros2013-12-04-0/+48
| | | | | | Add platform glue logic for the SATA controller. Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: OMAP5: Add PRCM and Control information for SATARoger Quadros2013-12-04-0/+6
| | | | | | | Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: DRA: EMIF: Change DDR3 settings to use hw levelingSRICHARAN R2013-12-04-0/+1
| | | | | | | | | | Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* Merge branch 'iu-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-09-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
| * ARM: OMAP5: DDR3: Change io settingsSRICHARAN R2013-11-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change from 0x64656465 to 0x64646464 is to remove the weak pull enabled on DQS, nDQS lines. This pulls the differential signals in the same direction which is not intended. So disabling the weak pulls improves signal integrity. On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being supplied a VREF! This was clearly a mistake. The second change improves the robustness of the interface and was specifically seen to cure corruption observed at high temperatures on some boards. With the above two changes better memory stability was observed with extended temperature ranges around 100C. Signed-off-by: Sricharan R <r.sricharan@ti.com>
| * dra7xx_evm: Enabled UART-boot mode and add dra7xx_evm_uart3 buildMinal Shah2013-11-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | UART booting is supported on this SoC, but via UART3 rather than UART1. Because of this we must change the board to use UART3 for all console access (only one UART is exposed on this board and a slight HW mod is required to switch UARTs). Signed-off-by: Minal Shah <minal.shah@ti.com> [trini: Make apply to mainline, reword commit] Signed-off-by: Tom Rini <trini@ti.com>
* | usb: dra7xx: Add support for dra7xx xhci USB hostDan Murphy2013-10-20-0/+4
| | | | | | | | | | | | | | | | | | | | | | Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | usb: omap: Move the xhci-omap header file to common locationDan Murphy2013-10-20-124/+0
| | | | | | | | | | | | | | Moving the xhci-omap header to a more global location so that other code can reference this code. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | OMAP5: USB: Add OMAP xHCI file and headerDan Murphy2013-10-20-0/+124
| | | | | | | | | | | | | | | | Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | ARM: OMAP5: Add registers and defines for USBOTG SSDan Murphy2013-10-20-0/+10
|/ | | | | | | Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* omap5: add qspi supportMatt Porter2013-10-07-0/+4
| | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* arm: omap5: echi: Add GPL-2.0+ SPDX-License-IdentifierNobuhiro Iwamatsu2013-09-20-14/+1
| | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-09-04-1/+10
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| * omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDRTom Rini2013-08-28-1/+10
| | | | | | | | | | | | | | | | | | After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART. Signed-off-by: Tom Rini <trini@ti.com>
* | ARM: OMAP5: USB: Add OMAP5 common USB EHCI informationDan Murphy2013-08-26-0/+60
| | | | | | | | | | | | | | | | * Enable the OMAP5 EHCI host clocks * Add OMAP5 EHCI register definitions * Add OMAP5 ES2 host revision Signed-off-by: Dan Murphy <dmurphy@ti.com>
* | SPDX-License-Identifier: fixing some problematic GPL-2.0 filesWolfgang Denk2013-08-19-18/+1
|/ | | | | | | | | | | | | | | | | Unlike the other patches in this series so far, this commit fixes a ambiguity in the license terms for some OMAP files: the code was originally derived from the Linux kernel sources, where it was clearly marked as GPL-2.0 (i. e. without the "or later" part), but the U-Boot version had a GPL-2.0+ file header added, apparently without permission / relicensing from the original authors of the code. Insert a GPL-2.0 SPDX-License-Identifier to fix this. Signed-off-by: Wolfgang Denk <wd@denx.de> cc: Tom Rix <Tom.Rix@windriver.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com>
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