arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	ARM: OMAP4470: Add voltage and dpll data	Taras Kondratiuk	2013-08-28	-1/+6
\| \| \| \| \| \| \| \| \| \| \| \| \|	OMAP4470 reference design uses TWL6032 PMIC with a following connection scheme: VDD_CORE = TWL6032 SMPS2 VDD_MPU = TWL6032 SMPS1 VDD_IVA = TWL6032 SMPS5 Set voltage and frequency values according to OMAP4470 Data Manual Operating Condition Addendum v0.7 Signed-off-by: Taras Kondratiuk <taras@ti.com>
*	Add GPL-2.0+ SPDX-License-Identifier to source files	Wolfgang Denk	2013-07-24	-17/+1
\| \| \| \| \| \|	Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
*	ARM: DRA7xx: clocks: Update PLL values	Lokesh Vutla	2013-06-10	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
*	ARM: DRA7xx: Correct the SYS_CLK to 20MHZ	Sricharan R	2013-06-10	-0/+4
\| \| \| \| \| \| \| \| \| \|	The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
*	ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h	Lokesh Vutla	2013-06-10	-0/+257
	To be consistent with other ARM platforms, renaming asm/arch-omap/clocks.h to asm/arch-omap/clock.h Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>