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path: root/arch/arm/include/asm/arch-omap3/mem.h
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* ARMV7: Fix duplicate use of "b" parameter in ACTIM_CTRLA definitionPeter Barada2012-02-12-28/+29
| | | | | | | | ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS() instead of "c". To make usage more clear, replace all single-letter macro parameters with more descriptive parameter names. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
* overo: add SPL supportAndreas Müller2012-01-16-0/+26
| | | | | | | | | | * implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard * run-tested with x-loader Signed-off-by: Andreas Müller <schnitzeltony@gmx.de> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add SPL support to omap3_evmTom Rini2011-12-06-0/+26
| | | | | | | Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add SPL support to BeagleboardTom Rini2011-12-06-0/+29
| | | | | | | | | | | | | | | | | | This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000. Cc: Dirk Behme <dirk.behme@gmail.com> Beagleboard rev C5, xM rev A: Tested-by: Tom Rini <trini@ti.com> Beagleboard xM rev C: Tested-by: Matt Ranostay <mranostay@gmail.com> Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3 SPL: Rework memory initalization and devkit8000 supportTom Rini2011-12-06-26/+0
| | | | | | | | | This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1. Cc: Frederik Kriewitz <frederik@kriewitz.eu> Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Suffix all Micron memory timing parts with their speedTom Rini2011-12-06-10/+11
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: Add optimal SDRC autorefresh control valuesTom Rini2011-12-06-5/+11
| | | | | | | | This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value. Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Add MCFG helper macroTom Rini2011-12-06-16/+30
| | | | | | | | | This adds an MCFG macro to calculate the correct value, similar to the ACTIMA/ACTIMB macros and adds a comment that all of the potential values here are documented in the TRM. Then we convert the Micron value to use this macro. Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Comment enable_gpmc_cs_config moreTom Rini2011-12-06-0/+4
| | | | | | | Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers. Signed-off-by: Tom Rini <trini@ti.com>
* omap3: mem: Move comments next to definitionsSanjeev Premi2011-11-04-76/+35
| | | | | | | | | | | | | Calculations for ACTIM_CTRLA amd ACTIM_CTRLB values are defined in 'header' style comments. Moved them along with definitions. Should help maintain consistency between comments and code if any of these are tweaked in future. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: mem: Clean-up whitespacesSanjeev Premi2011-11-04-26/+26
| | | | | | | | | Consistent use of TABs and align definitions with neighbouring code. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: mem: Define and use common macrosSanjeev Premi2011-11-04-24/+62
| | | | | | | | | | | | | Define common macros to arrive at the values of registers SDRC_ACTIM_CTRLA and SDRC_ACTIM_CTRLB for different memory types. This doesn't make any real change in the execution but helps readability. Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: Configure RAM bank 0 if in SPLSimon Schwarz2011-09-30-0/+36
| | | | | | | | | | OMAP3 relied on the memory config done by X-loader or Configuration Header. This has to be reworked for the implementation of a SPL. This patch configures RAM bank 0 if CONFIG_SPL_BUILD is set. Settings for Micron-RAM used by devkit8000 are added to mem.h Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* OMAP3: SDRC: Introduce Numonyx DDR typeEnric Balletbo i Serra2010-10-17-0/+43
| | | | | | | | | | Introduce Numonyx DDR timings and provide CONFIG_OMAP3_NUMONYX_DDR config options to allow for platform files to setup their timings. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Acked-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: Consolidate SDRC related operationsVaibhav Hiremath2010-06-08-0/+13
| | | | | | | | | | | Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Move architecture-specific includes to arch/$ARCH/include/asmPeter Tyser2010-04-13-0/+273
This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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