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* imx: mx6 introuduce macro is_mx6dqpPeng Fan2015-06-27-0/+5
| | | | | | | | | | Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6 correct is_soc_rev usagePeng Fan2015-06-27-2/+2
| | | | | | | | is_soc_rev should return a bool value, so use "==", but not "-", change (is_soc_rev(CHIP_REV_1_0) > 0) to (soc_rev() > CHIP_REV_1_0). This patch also add space between "&" for cpu_type(rev) macro. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-0/+3
| | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
* imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-19-0/+1
| | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-19-0/+1
| | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* mx6: add OTP bank1 registersTim Harvey2015-05-19-0/+19
| | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: mx6sx enable SION for i2c pin muxPeng Fan2015-05-19-20/+20
| | | | | | | | | | | | Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise we will get erros when doing i2c operations. error log like the following: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0xb retry=1 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: mx6: ddr: add pd_fast_exit flag to system informationTim Harvey2015-04-22-0/+1
| | | | | | | | | | | DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit. In slow-exit mode the DLL is off but in some quiescent state that makes it easy to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK). In fast-exist mode the DLL is maintained such that it is ready again in about 3tCK. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx6: Added DEK blob generator commandRaul Cardenas2015-03-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's SEC block has built-in Data Encryption Key(DEK) Blob Protocol which provides a method for protecting a DEK for non-secure memory storage. SEC block protects data in a data structure called a Secret Key Blob, which provides both confidentiality and integrity protection. Every time the blob encapsulation is executed, a AES-256 key is randomly generated to encrypt the DEK. This key is encrypted with the OTP Secret key from SoC. The resulting blob consists of the encrypted AES-256 key, the encrypted DEK, and a 16-bit MAC. During decapsulation, the reverse process is performed to get back the original DEK. A caveat to the blob decapsulation process, is that the DEK is decrypted in secure-memory and can only be read by FSL SEC HW. The DEK is used to decrypt data during encrypted boot. Commands added -------------- dek_blob - encapsulating DEK as a cryptgraphic blob Commands Syntax --------------- dek_blob src dst len Encapsulate and create blob of a len-bits DEK at address src and store the result at address dst. Signed-off-by: Raul Cardenas <Ulises.Cardenas@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ulises Cardenas <ulises.cardenas@freescale.com> Signed-off-by: Ulises Cardenas-B45798 <Ulises.Cardenas@freescale.com>
* imx: mx6sl: Extend USDHC SD2 pins to support 8-wire useOtavio Salvador2015-02-23-0/+5
| | | | | | This adds the DATA[4-7] and RST pin definitions. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* imx:mx6sl add I2c pad settingsPeng Fan2015-02-23-0/+5
| | | | | | A few pad settings are I2C1 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-17-0/+2
| | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* imx: mx6: Fixed AIPS3 base address issueYe.Li2015-02-10-2/+2
| | | | | | | | | Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx:mx6 update fuse_bank0_regsPeng Fan2015-02-10-4/+8
| | | | | | Update fuse_bank0_regs structure according reference mannual. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6sx add dram io configure for mx6sxPeng Fan2015-01-22-0/+46
| | | | | | | | | | | Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm:mx6sx add QSPI supportPeng Fan2014-12-31-6/+7
| | | | | | | Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2014-12-11-0/+5
|\ | | | | | | | | | | | | Conflicts: board/freescale/mx6sxsabresd/mx6sxsabresd.c Signed-off-by: Tom Rini <trini@ti.com>
| * imx:mx6slevk add board level support for usbPeng Fan2014-11-14-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return USB_INIT_HOST to let host port work in host mode. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye Li <B37916@freescale.com>
* | arm: mx6: Change defines ENET_xxMHz to ENET_xxMHZ (no CamelCase)Stefan Roese2014-12-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | As checkpatch complaines about these camel-case defines, lets change them to only use upper-case characters. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | arm: mx6: introduce disable_sata_clockNikita Kiryanov2014-11-24-0/+1
| | | | | | | | | | | | | | Implement disable_sata_clock for mx6 SoCs. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de>
* | mx6: clock: Add thermal clock enable functionNitin Garg2014-11-21-0/+1
| | | | | | | | | | | | | | | | Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* | mx6: add weim registersFabio Estevam2014-11-20-0/+37
| | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | imx: consolidate set_chipselect_size functionFabio Estevam2014-11-20-0/+1
|/ | | | | | | | | | Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: mx6sl: Add IOMUX setting for USDHC1-3Ye.Li2014-11-03-0/+19
| | | | | | Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-11-03-0/+2
| | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
* arm: arch-mx6: typo fixes in crm_regs.hSoeren Moch2014-10-30-4/+4
| | | | | | fix typos in video pll related register names and bit defines Signed-off-by: Soeren Moch <smoch@web.de>
* arm: imx6: fix typos in CCM_ANALOG_PLL_VIDEO_DENOM register nameAnatolij Gustschin2014-10-30-1/+1
| | | | | | Fix name for Video PLL denominator register. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* imx6sx: Fix i.MX6SX HAB api function table offsetNitin Garg2014-10-01-5/+11
| | | | | | | | | i.MX6SX ROM implements unified table sections. The HAB function table is at offset 0x100. Update the HAB function pointers accordingly. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* usb: ehci-mx6: Rename the USB register base addressYe.Li2014-09-29-7/+2
| | | | | | | | | | | | The mx6sl/mx6sx has 2 OTG and 1 host. So they have name "USBO2H_USB_BASE_ADDR" in imx-regs.h. The driver hard codes the USB base address name to "USBOH3", which causes the driver failed to build for mx6sl/mx6sx. This patch uniform the address name to "USB_BASE_ADDR" for all mx6 series. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: Support i.MX6 High Assurance Boot authenticationNitin Garg2014-09-22-0/+1
| | | | | | | | | | | | When CONFIG_SECURE_BOOT is enabled, the signed images like kernel and dtb can be authenticated using iMX6 CAAM. The added command hab_auth_img can be used for HAB authentication of images. The command takes the image DDR location, IVT (Image Vector Table) offset inside image as parameters. Detailed info about signing images can be found in Freescale AppNote AN4581. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* pcie_imx: Add mx6solox supportFabio Estevam2014-09-09-0/+9
| | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* mx6: imx-regs: Provide a structure for GPC registersFabio Estevam2014-09-09-0/+13
| | | | | | | Introduce a structure for accessing the General Power Controller block (GPC) registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm: mx6: add get_cpu_type()Nikita Kiryanov2014-09-09-2/+3
| | | | | | | | Define get_cpu_type(). Reuse it in is_cpu_type(). Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mx6: add clock enabling functionsNikita Kiryanov2014-09-09-0/+5
| | | | | | | | | Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* mx6sxsabresd: Add Ethernet supportFabio Estevam2014-08-20-0/+11
| | | | | | | | mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031. Add support for one FEC port initially. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: add support of multi-processor commandGabriel Huau2014-08-20-0/+14
| | | | | | | | | This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: crm_regs: Fix MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADEDFabio Estevam2014-08-08-1/+1
| | | | | | | According to the Reference Manual the 'mask_periph2_clk_sel_loaded' field of register CCM_CIMR corresponds to bit 19 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: crm_regs: Fix MXC_CCM_CLPCR_WB_PER_AT_LPM definitionFabio Estevam2014-08-08-1/+1
| | | | | | | According to the Reference Manual the 'wb_per_at_lpm' field of register CCM_CLPCR corresponds to bit 16 so fix its definition accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: crm_regs: Fix CDCDR_SPDIF0_CLK_PODF mask and offsetFabio Estevam2014-08-08-2/+2
| | | | | | | | According to the Reference Manual the 'spdif0_clk_podf' field of register CCM_CDCDR corresponds to bits 22, 23 and 24, so fix the mask and offset definitions accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: imx-regs: Remove unused 'omux' field from iomux structFabio Estevam2014-08-08-2/+0
| | | | | | | | | | 'omux' field is not used anywhere and such layout is not valid for mx6solox. Instead of adding more ifdef's into the structure, let's simply remove this unused 'omux' field. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: add enable_spi_clk()Heiko Schocher2014-07-23-0/+2
| | | | | | | | | add enable_spi_clk(), so board code can enable spi clocks. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Stefano Babic <sbabic@denx.de>
* i.MX6: define struct pwm_regs and PWMCR_* definesHeiko Schocher2014-07-23-0/+16
| | | | | | | add defines for pwm modul found on imx6. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* imx6: add gpr2 usb_otg_id iomux select control defineHeiko Schocher2014-07-23-0/+2
| | | | | | | | add IOMUXC_GPR1_USB_OTG_ID_OFFSET and IOMUXC_GPR1_USB_OTG_ID_SEL_MASK define for the USB_OTG_ID_SEL bit. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: Adjust the GPR offset for mx6soloxFabio Estevam2014-07-23-0/+3
| | | | | | | On mx6solox there is an additional 0x4000 offset for the GPR registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: Remove duplication of iomuxc structureFabio Estevam2014-07-23-9/+0
| | | | | | | | | | | | | | | There is no need to keep iomuxc_base_regs structure as it serves the exact same purpose of the iomuxc structure, which is to provide access to the GPR registers. The additional fields of iomuxc_base_regs are not used. Other advantage of 'iomuxc' is that it has a shorter name and the variable declarations can fit into a single line. So remove iomuxc_base_regs structure and use iomuxc instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6sx: Add pin definitionsFabio Estevam2014-07-10-0/+1677
| | | | | | Add the pin definitions for mx6sx. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Add support for the mx6solox variantFabio Estevam2014-07-10-4/+337
| | | | | | | | | | | | mx6solox is the newest member of the mx6 family. Some of the new features on this variants are: - Cortex M4 microcontroller (besides the CortexA9) - Dual Gigabit Ethernet Add the initial support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10Eric Nelson2014-07-10-2/+2
| | | | | | | | | | | | | | | The pad settings for DISP0_DATA02 and DISP0_DAT10 were not set in the same way as DISP0_DAT00-23, causing much flicker in parallel RGB displays on Dual-Lite and Solo processors. These settings now match the i.MX6 Dual and Quad core versions. Note that this fixes a regression in commit b47abc3 and that this is the second time we've had a regression on these two pads (See commit e654ddf). Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx: correct HAB status for new chip TOStefano Babic2014-06-17-7/+16
| | | | | | | | | | | | | | | | | | | | According to: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0 ENGR00287268 mx6: fix the secure boot issue on the new tapout chip commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b newer i.MX6 silicon revisions have an updated ROM and HAB API table. Please see also: i.MX Applications Processors Documentation Engineering Bulletins EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison With this change the secure boot status is correctly displayed Signed-off-by: Stefano Babic <sbabic@denx.de>
* mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RCFabio Estevam2014-06-17-1/+1
| | | | | | | | | | | | mx6 reference manual incorrectly states that the DEVICE_TYPE field of IOMUXC_GPR12 register should be configured as '0010' for setting the PCI controller in RC mode. The correct value should be '0100' instead. This also aligns with the same value used in the mx6 pci kernel driver. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-10-18 12:31:00 +0000