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* spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+1
| | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* Add initial support for Wandboard dual lite and solo.Fabio Estevam2013-03-20-0/+3
| | | | | | | | | Wandboard is a development board that has two variants: one version based on mx6 dual lite and another one based on mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Provide a structure for accessing HDMI registersFabio Estevam2013-03-07-536/+547
| | | | | | | | Provide a structure for accessing HDMI registers, so that we can use proper read/write accessors. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: Add DDR controller registersEric Nelson2013-03-07-0/+225
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6DL: define IOMUX pads NANDF_CS1-3 for use as GPIOEric Nelson2013-03-07-0/+3
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: crm_regs: define IOMUXC_GPR4/6/7Eric Nelson2013-03-07-0/+5
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: crm_regs: define CCM_CCGRx for use in board config filesEric Nelson2013-03-07-0/+12
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: consolidate pad names for multi-CPU boardsEric Nelson2013-03-07-1766/+1797
| | | | | | | | | | | Rename all i.MX6 pad declarations to MX6_PAD_x, so a board may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo (MX6DL) by including the proper header. Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd only support MX6Q, so they include mx6q_pins.h. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mx6: Disable Power Down Bit of watchdogFabio Estevam2013-02-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* arch-mx6: add mx6dl_pins.hTroy Kisky2012-11-10-0/+149
| | | | | | | Only the values used in the sabrelite board are added currently. Add more as other boards use them. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* imx-common: cpu: add imx_ddr_sizeTroy Kisky2012-11-10-0/+1
| | | | | | | | | | Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky2012-11-10-1/+10
| | | | | | | | | | Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* i.MX6: add HDMI transmitter register declarations from kernel WIP.Eric Nelson2012-10-16-0/+1053
| | | | | | | | Original source from Pengutronix HDMI driver work: http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commitdiff;h=72c31cd67ac880bd90785af86f8e46f8ea7b3bb0 Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: set drive strength for parallel RGB padsEric Nelson2012-10-16-29/+29
| | | | | | Default drive strength is disabled and won't function. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* mx6qsabreauto: Pass the board revision to the kernelFabio Estevam2012-10-16-0/+6
| | | | | | | | | | | The kernel from Freescale expects that the bootloader passes the board revision. Read the board revision and pass it via get_board_rev(). Without passing the board revision the kernel does not operate properly as the initialization of peripherals are different in revA versus revB boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-0/+14
| | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-0/+1
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: get rid of redundant struct src_regs (dupe of struct src)Eric Nelson2012-10-15-21/+0
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: define struct iomuxc and IOMUX_GPR2 register bitfieldsEric Nelson2012-10-15-0/+73
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: Add ANATOP_PFD_480 bitfield constantsEric Nelson2012-10-15-0/+24
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: define IOMUX_GPR3 register bitfieldsEric Nelson2012-10-15-0/+48
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: define bitfields for CHSCCDR registerEric Nelson2012-10-15-0/+4
| | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: change register name for CCM_CHSCCDR to match ref. manualEric Nelson2012-10-15-1/+1
| | | | | | | Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in reference manual, but was named chscdr in struct mxc_ccm_reg. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.MX6: provide functional names for CCM_CCGR0-CCGR6 bit fieldsEric Nelson2012-10-15-179/+179
| | | | | | | | | | | | | Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/ Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* MX6: drop binary constants from iomux headerStefano Babic2012-09-17-62/+62
| | | | | | | | | | | | | | | | Constants set with binary value (0b...) are not compiled from old toolchain when used by the clrsetbits_le32 macro. Replaces them with the corresponding hex value. The error reported (for example with the mx6qsabrelite board) is something like: mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant Signed-off-by: Stefano Babic <sbabic@denx.de>
* mxc: Define architecture identifierBenoît Thébaudeau2012-09-01-0/+2
| | | | | | | | | | | | | Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
* MX: Set a common gpio.h for all i.MXStefano Babic2012-09-01-8/+1
| | | | | | | | | Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
* imx-common/cmd_bmode.c: add imx bmode (bootmode) commandTroy Kisky2012-09-01-0/+21
| | | | | | | | | | | | This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
* iomux: move IOMUX_GPR13_xxx definesTroy Kisky2012-09-01-0/+129
| | | | | | | Move mx6 specific defines to arch-mx6 directory. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx-common: add i2c.c for bus recovery supportTroy Kisky2012-07-31-0/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* i.mx: iomux-v3.h: move to imx-common include directoryTroy Kisky2012-07-31-215/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: Make pad name macro consistent with the datasheetAshok2012-07-20-2/+2
| | | | | | | | Use the same name as defined in the datasheet. DSP_CLK -> DISP_CLK Signed-off-by: Ashok Kumar Reddy Kourla <ashokkourla2000@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-10-0/+3
| | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctlyJason Liu2012-07-07-2/+2
| | | | | | | | | If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct Signed-off-by: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: add enable_sata_clock()Eric Nelson2012-05-15-0/+121
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Stefano Babic <sbabic@denx.de>
* i.MX6: Add ANATOP regulator initDirk Behme2012-05-15-0/+2
| | | | | | | | | | | | | | | | Init the core regulator voltage to 1.2V. This is required for the correct functioning of the GPU and when the ARM LDO is set to 1.225V. This is a workaround to fix some memory clock jitter. Note: This should be but can't be done in the DCD. The bootloader prevents access to the ANATOP registers. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> CC: Jason Chen <b02280@freescale.com> CC: Jason Liu <r64343@freescale.com> CC: Ranjani Vaidyanathan <ra5478@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <festevam@gmail.com>
* imx-common: Factor out get_ahb_clk()Fabio Estevam2012-05-15-2/+3
| | | | | | | | | get_ahb_clk() is a common function between mx5 and mx6. Place it into imx-common directory. Cc: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Remove unneeded/repititive definitions from imx headersVikram Narayanan2012-04-16-2/+0
| | | | | | | Remove gpio related unused/repititive definitions from imx headers. Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.MX6: define CACHELINE_SIZEEric Nelson2012-04-16-0/+2
| | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mx6: Read silicon revision from registerFabio Estevam2012-03-27-0/+142
| | | | | | | | | | | | | | | Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* mx6: Remove duplicate definition of ANATOP_BASE_ADDRFabio Estevam2012-03-27-1/+0
| | | | | | Remove duplicate definition of ANATOP_BASE_ADDR. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* usb/ehci: Add USB support for the MX6QWolfgang Grandegger2012-03-26-0/+4
| | | | | | | Currently, only USB Host 1 is supported. Cc: Remy Bohmer <linux@bohmer.net> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* net: fec_mxc: add 1000 Mbps selectionTroy Kisky2012-02-27-0/+1
| | | | | | | | Define FEC_QUIRK_ENET_MAC and add to arch-mx6/imx-regs.h Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* mx6q: Add support for ECSPI through mxc_spi driverEric Nelson2012-02-27-0/+44
| | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* mx6q: define GPIO macros for translating between ordinals and port:indexEric Nelson2012-02-27-0/+4
| | | | | | | | | | | | | | | | | The interface to the mxc_gpio driver uses integer (ordinal) values to refer to all GPIOs on the i.MX processors. The registers themselves and much of the i.MX documentation are banked in groups of 32, and these macros allow the use of the port:index numbering for clarity. GPIO_NUMBER() converts to ordinal value from port:index GPIO_PORT() returns the port of an ordinal value GPIO_INDEX() returns the index or offset of the ordinal. Discussion on the mailing list at http://lists.denx.de/pipermail/u-boot/2012-January/116927.html Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* i.mx6: mx6x_pins: Fix uart txd definitionsTroy Kisky2012-02-12-24/+12
| | | | | | | | | | | | | The uart txd pad can also provide the rxd function. But it does not stop its tx role. This could be used for a half duplex serial port. Change names to reduce confusion. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* imx: mx6q: add aipstz init for off platform periphJason Liu2012-01-16-0/+11
| | | | | | | | | | | | Init peripheral access control register of AIPSTZ OPACRx: Buffer Writes(BW): 0 -> not bufferable, Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses. Write Protect(WP): 0 -> allows write accesses. Trusted Protect(TP): 0 -> allows unstrusted master Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de>
* i.mx6:imx6q: allign MAC address with burned-in orderingJason Liu2012-01-16-1/+1
| | | | | | | | | | | | | | | | For the i.mx6q, the burned-in MAC address will be the following odering, fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5] fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4] fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3] fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2] fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1] fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0] This patch also fix the error caculation for the fuse bank[0] address Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Stefano Babic <sbabic@denx.de>
* net: imx: Add multi-FEC support for imx_get_mac_from_fuseFabio Estevam2012-01-16-1/+1
| | | | | | | | | | Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter. This feature is important on mx28 SoC for example that has two FEC ports. Cc: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* i.mx: add the initial support for freescale i.MX6Q processorJason Liu2011-12-09-0/+3037
i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor. Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc:Stefano Babic <sbabic@denx.de>
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