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* mx5: fix get_reset_causeStefano Babic2015-03-05-1/+0
| | | | | | | | | | | | commit d9f43c8f5c1d7ed27c99a06be85a4bb64b2c73fb sets get_reset_cause() as static, but this conflicts with mx5 where its prototype is in sys_proto.h. Drop it from sys_proto.h and drop print_cpuinfo from mx53_loco, factorizing the call for this board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Jason Liu <jason.hui@linaro.org>
* imx: consolidate set_chipselect_size functionFabio Estevam2014-11-20-10/+2
| | | | | | | | | | Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* ARM: mx5: Fix CHSCCDR nameMarek Vasut2014-08-20-1/+1
| | | | | | Fix the name of the CCM CHSCCDR register. Signed-off-by: Marek Vasut <marex@denx.de>
* spl: consolidate arch/arm/include/asm/arch-*/spl.hMasahiro Yamada2014-06-06-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/spl.h requires all SoCs to have arch/arm/include/asm/arch-*/spl.h. But many of them just define BOOT_DEVICE_* macros. Those macros are used in the "switch (boot_device) { ... }" statement in common/spl/spl.c. So they should not be archtecture specific, but be described as a simpile enumeration. This commit merges most of arch/arm/include/asm/arch-*/spl.h into arch/arm/include/asm/spl.h. With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h will be merged, while I am not sure about OMAP and Exynos. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com> CC: Stefano Babic <sbabic@denx.de> CC: Minkyu Kang <mk7.kang@samsung.com> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bo Shen <voice.shen@atmel.com> [on sama5d3xek board for at91 part] Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stefano Babic <sbabic@denx.de> [applying Tim's i.MX6 patches] Acked-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2014-02-21-3/+4
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| * spi: spi-mxc: add defines for clk inactive state for ECSPIMarkus Niebel2014-02-18-3/+4
| | | | | | | | | | | | | | | | | | Provide define for the SCLK_CTL field of the config reg of ECSPI. While at it, oder the defines to improve readability and make adding more defines easier. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | imx: Introduce a header for the imx cpu versionsFabio Estevam2014-02-11-6/+1
|/ | | | | | | Instead of duplicating the CPU definitions at mx5 and mx6 sys_proto.h header files, introduce a common header to centralize such definitions. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* arm: mx5: Add fuse supply enable in fsl_iimSergey Alyoshin2014-01-03-0/+4
| | | | | | | Enable fuse supply before fuse programming and disable after. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* usb: ehci-mx5: Use 'bool' instead of 'unsigned char'Fabio Estevam2013-08-26-3/+3
| | | | | | | The 'enable' argument can be better expressed as boolean. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-109/+7
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* imx: mx5: Remove legacy iomux supportBenoît Thébaudeau2013-05-05-970/+0
| | | | | | | | Legacy iomux support is no longer needed now that all boards have been converted to iomux-v3. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Marek Vasut <marex@denx.de>
* imx: iomux-v3: Add iomux-mx53.hBenoît Thébaudeau2013-05-05-0/+1232
| | | | | | | | Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX53. The content of the file is taken from Freescale's Linux kernel at commit 4ab3715, plus the required changes to make it work in U-Boot. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: iomux-v3: Add missing definitions to iomux-mx51.hBenoît Thébaudeau2013-05-05-27/+124
| | | | | | | | Add missing definitions that are required by future changes. By the way, make some cosmetic cleanup. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: iomux-mx51: Fix MX51_PAD_EIM_CS2__GPIO2_27Benoît Thébaudeau2013-05-05-1/+1
| | | | | | | In ALT1 mode, EIM_CS2 is GPIO2[27], not ESDHC1.CD. Hence, rename MX51_PAD_EIM_CS2__SD1_CD to MX51_PAD_EIM_CS2__GPIO2_27. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* arm: mx5: Add NAND clock handlingMarek Vasut2013-05-05-0/+1
| | | | | | | | | | | | | Augment the MX5 clock code with function to enable and configure NFC clock. This is necessary to get NFC working on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* arm: mx5: Add SPL support code to MX5Marek Vasut2013-05-05-0/+19
| | | | | | | | | | | | Fix minor adjustments needed to get SPL framework building on MX5. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* imx: iomux-v3: Include PKE and PUE to pad control pull definitionsBenoît Thébaudeau2013-04-28-6/+4
| | | | | | | | | | | | | | | | | PUE requires PKE to mean something, as do pull values with PUE, so do not compell users to explicitly use PKE and PUE everywhere. This is also what is done on Linux and what has already been done for i.MX51. By the way, remove some unused pad control definitions. There is no change of behavior. Note that SPI_PAD_CTRL was defined by several boards with a pull value, but without PKE or PUE, which means that no pull was actually enabled in the pad. This might be a bug in those boards, but this patch does not change the behavior, so it just removes the meaningless pull value from those definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: iomux-v3: Fix common pad control definitionsBenoît Thébaudeau2013-04-28-23/+0
| | | | | | | | | | | | | Commit dc88403 "iomux-v3: Place pad control definitions into common file" broke mx51_efikamx because it made i.MX6's pad control definitions conflict with i.MX51's. i.MX51's pad control definitions are actually common to some other i.MX (25/35/53), so move them to the common iomux-v3.h (just like what is done in Linux's), and select the correct definitions depending on whether CONFIG_MX6 is defined or not. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: Add useful fuse definitionsBenoît Thébaudeau2013-04-28-1/+15
| | | | | | Define the UID (SoC unique ID) fuses, and the fuses available for the user. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* imx: Homogenize and fix fuse register definitionsBenoît Thébaudeau2013-04-28-1/+5
| | | | | | | | | | | | | | | | | | IIM: - Homogenize prg_p naming (the reference manuals are not always self-consistent for that). - Add missing SCSx and bank registers. - Fix the number of banks on i.MX53. OCOTP: - Rename iim to ocotp in order to avoid confusion. - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the reference manual. - Merge the existing spinoff gp1 fuse definition on i.MX6. - Fix the number of banks on i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx53ard: Move register masks into imx-regs.hFabio Estevam2013-04-25-0/+2
| | | | | | | imx-regs.h is more appropriate location for containing register masks. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+1
| | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx31/mx35/mx51/mx53/mx6: add watchdogTroy Kisky2013-01-13-10/+0
| | | | | | | Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Align SPI CS naming with i.MX53 reference manualFabio Estevam2012-11-19-3/+3
| | | | | | Align SPI chip select naming with i.MX53 reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx-common: cpu: add imx_ddr_sizeTroy Kisky2012-11-10-0/+1
| | | | | | | | | | Read memory setup registers to determine size of available ram. This routine works for mx53/mx6x I need this because when mx6solo called get_ram_size with a too large maximum size, the system hanged. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololiteTroy Kisky2012-11-10-1/+8
| | | | | | | | | | Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx5: lowlevel_init.S: Fix PLL settings for mx53Fabio Estevam2012-10-17-0/+4
| | | | | | | | | | | | | | | | | | Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the requested frequency. Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its maximum frequency. Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little bit to allow easier comparison with the original clock setup from FSL U-boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx5/6 clocks: Fix SDHC clocksBenoît Thébaudeau2012-10-15-0/+4
| | | | | | | | | | | | | | | | The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
* mx5 clocks: Fix get_lp_apm()Benoît Thébaudeau2012-10-15-0/+15
| | | | | | | | | | | | If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: Add and use CCSR definitionsBenoît Thébaudeau2012-10-15-0/+23
| | | | | | | This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx51: Fix USB PHY clocksBenoît Thébaudeau2012-10-15-1/+2
| | | | | | | | | | | | | | | The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
* mx5: Fix clock gate valuesBenoît Thébaudeau2012-10-15-0/+3
| | | | | | | | | The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5: Use explicit clock gate namesBenoît Thébaudeau2012-10-15-4/+275
| | | | | | | | Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5 clocks: CleanupBenoît Thébaudeau2012-10-15-6/+93
| | | | | | | | | | Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* mx5/6: Define default SoC input clock frequenciesBenoît Thébaudeau2012-10-15-0/+14
| | | | | | | | | | | Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-15-0/+1
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mx51evk: Add CONFIG_REVISION_TAGBenoît Thébaudeau2012-09-23-0/+2
| | | | | | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. If this data is not present, the kernel misconfigures the TZIC, which results in the timer interrupt handler never being called, so the kernel deadlocks while calibrating its delay. Suggested-by: Greg Topmiller <Greg.Topmiller@jdsu.com> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* mxc: Define architecture identifierBenoît Thébaudeau2012-09-01-0/+2
| | | | | | | | | | | | | Define ARCH_MXC for i.MX devices. This is useful to identify features or behaviors common to all i.MX SoCs. The i.MX28 is omitted because its architecture is a bit different (like imx/mxc vs. mxs in Linux). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com>
* mx5: add iomux-mx51.h includeMatt Sealey2012-09-01-0/+164
| | | | | | | | | | | | | | | | | | | | Allow usage of the imx-common/iomux-v3.h framework by including pad settings for the i.MX51. The content of the file is taken from Linux kernel at commit 5d23b39 plus the required changes to make it work in U-Boot. The contained pad settings are the minimum required to make an Efika MX boot and get all the currently-implemented peripherals working in U-Boot. It is recommended that this file not be just a dumping ground for pins but only contain the settings required for all the boards using it. Changes for v2: * reference commit id from Linux kernel * additionally roll in the USB pads * removed GPIO_NUMBER define Signed-off-by: Matt Sealey <matt@genesi-usa.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Undeclare imx_decode_pll()Benoît Thébaudeau2012-09-01-2/+0
| | | | | | | The imx_decode_pll() function does not exist for mx5, so remove its declaration. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
* MX: Set a common gpio.h for all i.MXStefano Babic2012-09-01-6/+1
| | | | | | | | | Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
* imx-common/cmd_bmode.c: add imx bmode (bootmode) commandTroy Kisky2012-09-01-0/+18
| | | | | | | | | | | | This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
* imx-common: add i2c.c for bus recovery supportTroy Kisky2012-07-31-0/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* i.mx53: add definition for I2C3_BASE_ADDRTroy Kisky2012-07-31-0/+1
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-10-2/+0
| | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx53: Allow IPUv3 driver to also work on mx53Fabio Estevam2012-05-25-2/+6
| | | | | | | Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchangedStefano Babic2012-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by: David Jander <david.jander@protonic.nl> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Jander <david.jander@protonic.nl> Acked-by: David Jander <david.jander@protonic.nl> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* mx53loco: Add CONFIG_REVISION_TAGFabio Estevam2012-05-15-0/+5
| | | | | | | | | | | FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information. The kernel uses this data to distinguish between Dialog versus mc34708 based boards, and also to distinguish between revA and revB of the mc34708 based boards. Suggested-by: Yu Li <yk@magniel.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx53loco: Allow to print CPU information at a later stageFabio Estevam2012-05-15-0/+1
| | | | | | | | | | | Print CPU information within board_late_init(). This is in preparation for adding 1GHz support, which requires programming a PMIC via I2C. As I2C is only available after relocation, print the CPU information later at board_late_init(), so that the CPU frequency can be printed correctly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx5: Add clock config interfaceFabio Estevam2012-05-15-1/+10
| | | | | | | | | | | mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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