arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	DMC: Exynos5: Enable update mode for DREX controller	Alim Akhtar	2014-11-17	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	Exynos5420: DMC: Add software read leveling	Akshay Saraswat	2014-06-13	-0/+3
\| \| \| \| \| \| \| \| \| \| \| \| \|	Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	Exynos5420: Add DDR3 initialization for 5420	Rajeshwari Birje	2013-12-30	-0/+10
\| \| \| \| \| \| \| \| \|	This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	EXYNOS5420: Add dmc and phy_control register structure	Rajeshwari Birje	2013-12-30	-0/+167
\| \| \| \| \| \| \| \|	Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0	Rajeshwari Shinde	2012-09-01	-0/+65
\| \| \| \| \| \| \| \|	The patch adds the memory initialization sequence of DDR3. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	EXYNOS: Add structure for Exynos4 DMC	Chander Kashyap	2012-03-27	-0/+109
\| \| \| \| \| \| \|	Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC). Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*	ARM: EXYNOS: Add support for Exynos5 based SoCs	Chander Kashyap	2012-02-12	-0/+146
	Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>